ntsc_gen.vhd

NTSC信号发生器VHDL源码。输出为BT656格式

library IEEE; 
--library virtex2; 
use IEEE.std_logic_1164.all;
use IEEE.std_logic_UNSIGNED.all;
--use virtex2.components.all;
-- synthesis translate_off
library unisim;
use unisim.vcomponents.all;
-- synthesis translate_on 
entity vid_enc_if is
	port (
		-- ITU-T BT.656 if
		-- input
		reset    : in std_logic;
		vid_27mhz_output_clock	            : in std_logic;
		-- output 
		ycrcb_p: out std_logic_vector(9 downto 0);
		PAL_NTSCN: out std_logic;
		TV_OUT_HSYNCH_N: out std_logic;
		TV_OUT_VSYNCH_N: out std_logic;
		tv_out_blank_n: out std_logic;
		-- buffer interface
		--buf_addr: out std_logic_vector( 11 downto 0);
		buf_update:out std_logic;
		buf_ind:out std_logic
	);
end vid_enc_if;

architecture imp of vid_enc_if is

signal h_clock: std_logic;
signal v_clock: std_logic;
signal sample_count:std_logic_vector( 1 downto 0);
signal h_count: std_logic_vector( 10 downto 0);
signal v_count: std_logic_vector( 9 downto 0);
signal v1_count:std_logic_vector( 9 downto 0);
signal vsync, hsync,fsync:std_logic;
signal col_0,col_68:std_logic;
signal pref:std_logic_vector(3 downto 0);
signal psel:std_logic_vector( 2 downto 0);
begin
	PAL_NTSCN<='0';
	--TV_OUT_HSYNCH_N <=not hsync; 
	--TV_OUT_VSYNCH_N <= not vsync; 
	TV_OUT_VSYNCH_N <='1';	 
	TV_OUT_HSYNCH_N <='1';
	
	tv_out_blank_n<= '1'; --when v_count="1000001101" else '0'; --'1';
	
	sample_counter:process(vid_27mhz_output_clock)
	begin
		if (vid_27mhz_output_clock'event and vid_27mhz_output_clock='1') then		
			if(reset='1') then
				sample_count<="11";
				h_clock<='0';
			else
				if(sample_count="11") then
					sample_count<="00";
					h_clock<='1';
				else
					sample_count<=sample_count+1;
					h_clock<='0';
				end if;
			end if;
		end if;
	end process;
	
	
	hcounter:process(h_clock)
	begin
		if( reset='1') then
			h_count<="00110101100";	
			v_clock<='0';		
		else
			if(h_clock'event and h_clock='1') then  -- 0-428 counter, total 429 samples
				case h_count is
					when "00110101100" =>
						h_count<=(others=>'0');
						v_clock<='1';
					when "00000001000" =>
						v_clock<='0';
						h_count<=h_count+1;
					when others =>
						h_count<=h_count+1;
						v_clock<='0';					
				end case;
			end if;		
		end if;
	end process;
	
	vcounter:process(v_clock)
	begin
		if( reset='1') then
			-- for debug
			v_count<="00"&X"14";
			--v_count<=(others=>'0');--"0000000000";
			v1_count<=(others=>'0');
		else
			if(v_clock'event and v_clock='1') then  --1-525 counter
				if(v_count="1000001101") then --"1000001101"
					v_count<="0000000001";
					v1_count<="0000000001";
				else
					if(v1_count="0100000110") then
						v1_count<="0000000001";
					else
						v1_count<=v1_count+1;
					end if;
					v_count<=v_count+1;
				end if;
			end if;
		end if;
	end process;	
	
	
	
	col_0<= '1' when h_count="00000000000" else '0';
	col_68<='1' when h_count="00001000100" else '0';
	
	psel<=fsync&vsync&col_0;
	with psel select pref<=
		"0000" when "000",
		"1101" when "001",
		"1011" when "010",
		"0110" when "011",
		"0111" when "100",
		"1010" when "101",
		"1100" when "110",
		"0001" when others;
		
	--tclk<='0';
	process(vid_27mhz_output_clock)				
	begin
		if(reset='1') then
			vsync<='1';
			hsync<='0';
			--fsync<='1';
			-- for debug
			fsync<='0';
		elsif( vid_27mhz_output_clock'event and vid_27mhz_output_clock='0' ) then
			if( col_0='1') then-- eav				 
				 case sample_count is
				 	when "00" =>
				 		hsync<='1';
				 		ycrcb_p<=(others=>'1');
				 	when "11"=>
				 		ycrcb_p<='1'&fsync&vsync&'1'&pref&"00";
				 	when others=>
				 		ycrcb_p<=(others=>'0');
				 end case;
			elsif( col_68='1') then 				
				case sample_count is
				 	when "00" =>
				 		ycrcb_p<=(others=>'1');
				 		hsync<='0';
				 	when "11"=>
				 		ycrcb_p<='1'&fsync&vsync&'0'&pref&"00";
				 	when others=>
				 		ycrcb_p<=(others=>'0');
				 end case;
			elsif(hsync='1') then
				if (sample_count(0)='0') then
					ycrcb_p<="1000000000";
				else
					ycrcb_p<="0001000000";
				end if;				
			else
				if(sample_count(0)='0') then
					ycrcb_p<="1000000000";
				else
					--ycrcb_p<=v1_count(5 downto 0)&"1000";  --"1000000000";
					ycrcb_p<=h_count(5 downto 0)&"1000";
				end if;
			end if;
			case v_count is
				--when "0000000001" => -- line 1
				when "1000001101"=> -- line 525
					vsync<='1';
				--when "0000010100" => -- line 20
				when "0000010110"	=> -- line 22
					vsync<='0';
				--when "0100001000" => -- line 264
				when "0100000110" 	=> -- line 262
					vsync<='1';
				--when "0100011011" => -- line 283
				when "0100011101"	=> -- line 285
					vsync<='0';
				when "0000000100" => -- line 4
					fsync<='0';
				when "0100001010" => -- line 266
					fsync<='1';
				when others =>
					null;					
			end case;
		end if;
	end process;
end imp;