my_zbt_controller.vhd

ZBT内存控制器.支持OPB总线。VHDL源码

library IEEE; 
--library virtex2; 
use IEEE.std_logic_1164.all;
use IEEE.std_logic_UNSIGNED.all;

--use virtex2.components.all;
-- synthesis translate_off
library unisim;
use unisim.vcomponents.all;
-- synthesis translate_on 

entity my_opb_zbt_ctrl is
	  generic (
    C_BASEADDR      : std_logic_vector(0 to 31) := X"FF800000";
    C_HIGHADDR      : std_logic_vector(0 to 31) := X"FF9FFFFF";
    C_ZBT_ADDR_SIZE : integer                   := 19
    );
  port (
    OPB_Clk : in std_logic;
    OPB_Rst : in std_logic;

    -- OPB signals
    OPB_ABus    : in std_logic_vector(0 to 31);
    OPB_BE      : in std_logic_vector(0 to 3);
    OPB_RNW     : in std_logic;
    OPB_select  : in std_logic;
    OPB_seqAddr : in std_logic;
    OPB_DBus    : in std_logic_vector(0 to 31);
    ZBT_DBus    : out std_logic_vector(0 to 31);
    ZBT_errAck  : out std_logic;
    ZBT_retry   : out std_logic;
    ZBT_toutSup : out std_logic;
    ZBT_xferAck : out std_logic;

    -- ZBT Memory signals
    ZBT_Clk_FB    : in  std_logic;
    ZBT_Clk_FBOut : out std_logic;
    ZBT_Clk       : out std_logic;
    ZBT_OE_N      : out std_logic;
    ZBT_ADV_LD_N  : out std_logic;
    ZBT_LBO_N     : out std_logic;
    ZBT_CE1_N     : out std_logic;
    ZBT_CE2_N     : out std_logic;
    ZBT_CE2       : out std_logic;
    ZBT_RW_N      : out std_logic;
    ZBT_CKE_N     : out std_logic;
    ZBT_A         : out std_logic_vector(C_ZBT_ADDR_SIZE-1 downto 0);
    ZBT_BW_N      : out std_logic_vector(1 to 4);
    ZBT_IO_I      : in  std_logic_vector(0 to 31);
    ZBT_IO_O      : out std_logic_vector(0 to 31);
    ZBT_IO_T      : out std_logic;
    ZBT_IOP_I     : in  std_logic_vector(1 to 4);
    ZBT_IOP_O     : out std_logic_vector(1 to 4);
    ZBT_IOP_T     : out std_logic
    );
end my_opb_zbt_ctrl;

architecture beh of my_opb_zbt_ctrl is
	signal chip_select_1:std_logic;
	signal zbt_cs:std_logic;
	signal zbt_ctrl_state:std_logic_vector(2 downto 0);
	signal zbt_state_i:std_logic_vector(3 downto 0);
	signal iZBT_xferAck:std_logic;
	signal counter:std_logic_vector(4 downto 0);
begin
	-- 
	chip_select_1<='1' when OPB_ABus(0 to 11) = C_BASEADDR( 0 to 11) else '0';
	zbt_cs<=chip_select_1 and OPB_select;
	zbt_state_i<=zbt_ctrl_state&zbt_cs;
	--
	process(OPB_Rst,OPB_Clk)
	begin
		if(OPB_Rst='1') then
			zbt_ctrl_state<=(others=>'0');
			iZBT_xferAck<='0';
			ZBT_retry<='0';
			ZBT_toutSup<='0';
			counter<=(others=>'0');
		elsif(OPB_Clk'event and OPB_Clk='1') then
			ZBT_toutSup<=OPB_select and (not iZBT_xferAck);
			case zbt_state_i is			
				when "0011" =>
					if(counter="10011") then
						zbt_ctrl_state<="010";
					else
						counter<=counter+1;
					end if;
				when "0101" =>
					zbt_ctrl_state<="011";
					--ZBT_DBus<=OPB_ABus;
					iZBT_xferAck<='1';
				when "0111" =>
					zbt_ctrl_state<="000";
					iZBT_xferAck<='0';
				when others=>
					if(zbt_cs='1') then
						zbt_ctrl_state<="001";
						counter<=(others=>'0');
					else
						zbt_ctrl_state<="000";
						counter<=(others=>'0');
					end if;	
					--iZBT_xferAck<='0';	
			end case;
		end if;
	end process;
	ZBT_errAck<='0';
	ZBT_xferAck<=iZBT_xferAck;
	ZBT_DBus<=OPB_ABus when iZBT_xferAck='1' else (others=>'0');
	--ZBT signals
	ZBT_Clk_FBOut<=ZBT_Clk_FB;
	ZBT_Clk<=ZBT_Clk_FB;
	ZBT_CKE_N<='0';
	ZBT_OE_N<='1';
	ZBT_ADV_LD_N<='0';
	ZBT_LBO_N<='0';
	ZBT_CE1_N<='0';
	ZBT_CE2_N<='0';
	ZBT_CE2<='0';
	ZBT_RW_N<='1';
	ZBT_A<=(others=>'0');
	ZBT_BW_N<=(others=>'1');
	ZBT_IO_O<=ZBT_IO_I;
	ZBT_IO_T<='1';
	ZBT_IOP_O<=ZBT_IOP_I;
	ZBT_IOP_T<='1';
end beh;