man_v54.npl

xilinx reference design for 1553B BUS analyer using

JDF D
// Created by iSE ver 1.0
PROJECT Untitled
DESIGN man_v54 Normal
DEVKIT XCR3256XL CS280
FLOW XST VHDL
MODULE top_level.vhd
MODSTYLE top_level Normal
MODULE decode_man.vhd
MODSTYLE decode_man Normal
[STRATEGY-LIST]
Normal=True, 997647219
[Normal]
xplaMaxppe=vhdxst.xcrplaff3s71012a, Implementation.TASKfitDes, 997648470, 19
xplaMaxFanin=vhdxst.xcrplaff3s71012a, Implementation.TASKfitDes, 997648470, 19
xplaMaxbfi=vhdxst.xcrplaff3s71012a, Implementation.TASKfitDes, 997648470, 39