automake.log

xilinx reference design for 1553B BUS analyer using

iSE Auto-Make Log File
-----------------------

Updating: Implement Design

Starting: 'C:\Xilinx_WebPACK\bin\nt\chipsim.exe top_level._prj top_level.prj none'


Chipsim, Xilinx, Inc. 

Done: completed successfully.

Starting: 'C:\Xilinx_WebPACK\bin\nt\exewrap  -batch  -command _XSTClean.bat '


Done: completed successfully.

Starting: 'C:\Xilinx_WebPACK\bin\nt\xst.exe -ifn top_level.xst -ofn top_level.plg:tapkeep'



=========================================================================
----  Global Settings
Tmp directory                      : .
DUMPDIR                            : .
overwrite                          : YES

=========================================================================


XST D-27
Copyright (c) 1995-2000 Xilinx, Inc.  All rights reserved.

--> Parameter TMPDIR set to .
 
--> Parameter DUMPDIR set to .
 
--> Parameter overwrite set to YES
 
--> =========================================================================
---- Source Parameters
Input File Name                    : top_level.prj
Input Format                       : VHDL

---- Target Parameters
Output File Name                   : top_level.edn
Output Format                      : EDIF

---- Source Options
Entity Name                        : top_level
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Compact
HDL Verbose Level                  : 1
RAM Extraction                     : Yes
RAM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
Resolution Style                   : WIRE_MS

---- FSM Options
FSM Flip-Flop Type                 : D

---- Target Options
Family                             : 9500
Add IO Buffers                     : NO
Use Fast Output Buffers            : NO
Macro Generator                    : Macro+
MACRO Preserve                     : YES
XOR Preserve                       : YES
FF Optimization                    : YES
Flatten Hierarchy                  : YES
Clock Enable                       : YES

---- General Options
Optimization Criterion             : Area
Optimization Effort                : 1

=========================================================================

Setting FSM Encoding Algorithm to : OPT

Compiling vhdl file C:\Xilinx_WebPACK\data\webpack\genff.vhd in Library genff.
Entity <g_depc> (Architecture <behavioral>) compiled.
Entity <g_tpc> (Architecture <behavioral>) compiled.
Entity <g_latpc> (Architecture <behavioral>) compiled.
Compiling vhdl file C:\cool_mod\Man_1553_V54\decode_man.vhd in Library work.
Entity <decode_man> (Architecture <behave>) compiled.
Compiling vhdl file C:\cool_mod\Man_1553_V54\top_level.vhd in Library work.
Entity <top_level> (Architecture <behave>) compiled.

Analyzing Entity <top_level> (Architecture <behave>).
Entity <top_level> analyzed. Unit <top_level> generated.

Analyzing Entity <decode_man> (Architecture <behave>).
WARNING : (VHDL_0081). C:\cool_mod\Man_1553_V54\decode_man.vhd (Line 389). The following signals are missing in the process sensitivity list:
sm_address, sram_message_ptr, mdi1, mdi3, time_counter, rclock_count, clock_count, data1, data2, data_word_count, command_status, pwclock_count, data_error, man_word.
Entity <decode_man> analyzed. Unit <decode_man> generated.


Synthesizing Unit <decode_man>.
    Extracting finite state machine <FSM_0> for signal <main_curr_state>.
	-----------------------------------------------------------------------
	| States             | 11                                             |
	| Transitions        | 24                                             |
	| Inputs             | 10                                             |
	| Outputs            | 16                                             |
	| Reset type         | asynchronous                                   |
	| Encoding           | compact                                        |
	| State register     | D  flip-flops                                  |
	-----------------------------------------------------------------------
    Extracting 23-bit register for signal <sm_address>.
    Extracting 1-bit register for signal <mdi3>.
    Extracting 1-bit register for signal <mdi1>.
    Extracting 16-bit up counter for signal <time_counter>.
    Extracting 1-bit register for signal <mdi2>.
    Extracting 6-bit register for signal <clock_count>.
    Extracting 5-bit register for signal <pwclock_count>.
    Extracting 8-bit register for signal <rclock_count>.
    Extracting 1-bit register for signal <data1>.
    Extracting 1-bit register for signal <data2>.
    Extracting 1-bit register for signal <data3>.
    Extracting 23-bit register for signal <sram_message_ptr>.
    Extracting 16-bit register for signal <man_word>.
    Extracting 1-bit 2-to-1 multiplexer for internal node.
    WARNING : (ADVISOR__0001). Extracting 1-bit latch for signal <statemachine_oe>.
    WARNING : (ADVISOR__0001). Extracting 2-bit latch for signal <command_status>.
    WARNING : (ADVISOR__0001). Extracting 16-bit latch for signal <man_data>.
    WARNING : (ADVISOR__0002). Extracting 1-bit latch for internal node.
    Extracting 23-bit adder for internal node.
    Extracting 8-bit adder for internal node.
    Extracting 5-bit adder for internal node.
    Extracting 6-bit adder for internal node.
    Extracting 23-bit adder for internal node.
    Extracting 2-bit adder for internal node.
WARNING : (HDL__0002). Input <din_sec> is never used.
WARNING : (HDL__0003). Output <test_out> is never used.
WARNING : (HDL__0003). Output <led1_sel> is never used.
WARNING : (HDL__0003). Output <led2_sel> is never used.
WARNING : (HDL__0003). Output <led3_sel> is never used.
WARNING : (HDL__0003). Output <io6> is never used.
WARNING : (HDL__0003). Output <io7> is never used.
WARNING : (HDL__0003). Output <io8> is never used.
WARNING : (HDL__0003). Output <io9> is never used.
WARNING : (HDL__0003). Output <io42> is never used.
WARNING : (HDL__0003). Output <io44> is never used.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  87 D-type flip-flop(s).
	inferred  20 Latch(s).
	inferred   6 Adder/Subtracter(s).
	inferred   1 Multiplexer(s).
Unit <decode_man> synthesized.


Synthesizing Unit <top_level>.
    Extracting 1-bit register for signal <reset_command>.
    Extracting 16-bit 2-to-1 multiplexer for signal <mux_out>.
    Extracting tristate(s) for signal <d>.
    Extracting tristate(s) for signal <sp_d>.
    Extracting 1-bit 2-to-1 multiplexer for signal <sram_cs1n>.
    Extracting 1-bit 2-to-1 multiplexer for signal <rwn>.
    Extracting 1-bit 2-to-1 multiplexer for signal <oen>.
    Extracting 23-bit 2-to-1 multiplexer for signal <a>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred  42 Multiplexer(s).
	inferred  32 Tristate(s).
Unit <top_level> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Registers                        : 13
  6-bit register                   : 1
  5-bit register                   : 1
  8-bit register                   : 1
  1-bit register                   : 7
  23-bit register                  : 2
  16-bit register                  : 1
# Latches                          : 4
  1-bit latch                      : 2
  2-bit latch                      : 1
  16-bit latch                     : 1
# Counters                         : 1
  16-bit up counter                : 1
# Multiplexers                     : 6
  1-bit 2-to-1 multiplexer         : 4
  16-bit 2-to-1 multiplexer        : 1
  23-bit 2-to-1 multiplexer        : 1
# Adders/Subtractors               : 6
  8-bit adder                      : 1
  5-bit adder                      : 1
  6-bit adder                      : 1
  23-bit adder                     : 2
  2-bit adder                      : 1

=========================================================================

Optimizing FSM <FSM_0> with Compact encoding and D flip-flops.

Starting low level synthesis...

Optimizing unit <top_level> ...

Merging netlists...

=========================================================================
Final Results
Output File Name                   : top_level.edn
Output Format                      : edif
Optimization Criterion             : Area
Target Technology                  : 9500
Flatten Hierarchy                  : YES
Macro Preserve                     : YES
Macro Generation                   : Macro+
XOR Preserve                       : YES

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 5
  8-bit adder                      : 1
  5-bit adder                      : 1
  6-bit adder                      : 1
  2-bit adder                      : 1
  16-bit adder                     : 1

Design Statistics
# Edif Instances                   : 1132
# I/Os                             : 106

Other Data
.NCF file name                     : top_level.ncf

=========================================================================
 
--> 
Done: completed successfully.

Starting: 'C:\Xilinx_WebPACK\bin\nt\exewrap   -command C:\Xilinx_WebPACK\bin\nt\edif2blf.exe -i top_level.edn -o top_level.bl3'



Parsing File top_level.edn ...

Complete.

%% ERROR count: 0  WARNING count: 0


Done: completed successfully.

Starting: 'C:\Xilinx_WebPACK\bin\nt\exewrap -pre _xplaopt1.rsp  -command _xplaopt2.rsp '




Parsing...
.

Parsing file top_level.bl3 ...

Parsing file xplalib.xst ...
> WARNING 5615 Pin/Node 'CLK16' is not found in module  but 'clk16' is found.
	   Enable case insensitive matching.
..

Synthesizing and Optimizing...
.................................................................
> WARNING 2358  Dangling pin din_sec removed.
.............................
..............................
%% Network final ======> 213 Mcells, 8 FbNand, 484 PLApts, 4 Levels


%% ERROR count: 0  WARNING count: 2


Done: completed successfully.

Starting: 'C:\Xilinx_WebPACK\bin\nt\exewrap   -command C:\Xilinx_WebPACK\bin\nt\xplaopt @2200.rsp'
Original: 'C:\Xilinx_WebPACK\bin\nt\xplaopt -it blif -i top_level.blx -run f -log top_level.er3 -ot n -ctrl top_level.ctrl -dev XCR3256XL-7CS280 -bfi 39 -fbn 0 -pre try -vho time_sim.vhd'




Parsing...
.

Parsing file top_level.blx ...
> WARNING 5440 Pin/Node 'DIN_SEC' specified in the control/UCF/NCF file does not exist.
....
> WARNING 5615 Pin/Node 'A[0]' is not found in module  but 'a[0]' is found.
	   Enable case insensitive matching.
.

Fitting...
...............

%% ERROR count: 0  WARNING count: 2


Done: completed successfully.