top_level.edn

xilinx reference design for 1553B BUS analyer using

(edif top_level 
  (edifversion 2 0 0)
  (ediflevel 0)
  (keywordmap (keywordlevel 0))
(status
 (written
  (timeStamp 2001 08 13 15 06 45)
  (program " XST  EDIF NetWriter"
  (version "D-27"))
 )
)
  (Library DESIGNS
    (ediflevel 0)
    (technology (numberdefinition))
    (cell VCC  (celltype GENERIC)
      (view netlist (viewtype NETLIST)
        (interface
          (port P (direction OUTPUT))
        )
      )
    )
    (cell FDCE  (celltype GENERIC)
      (view netlist (viewtype NETLIST)
        (interface
          (port D (direction INPUT))
          (port C (direction INPUT))
          (port CLR (direction INPUT))
          (port CE (direction INPUT))
          (port Q (direction OUTPUT))
        )
      )
    )
    (cell AND2  (celltype GENERIC)
      (view netlist (viewtype NETLIST)
        (interface
          (port I0 (direction INPUT))
          (port I1 (direction INPUT))
          (port O (direction OUTPUT))
        )
      )
    )
    (cell INV  (celltype GENERIC)
      (view netlist (viewtype NETLIST)
        (interface
          (port I (direction INPUT))
          (port O (direction OUTPUT))
        )
      )
    )
    (cell AND3  (celltype GENERIC)
      (view netlist (viewtype NETLIST)
        (interface
          (port I0 (direction INPUT))
          (port I1 (direction INPUT))
          (port I2 (direction INPUT))
          (port O (direction OUTPUT))
        )
      )
    )
    (cell AND4  (celltype GENERIC)
      (view netlist (viewtype NETLIST)
        (interface
          (port I0 (direction INPUT))
          (port I1 (direction INPUT))
          (port I2 (direction INPUT))
          (port I3 (direction INPUT))
          (port O (direction OUTPUT))
        )
      )
    )
    (cell OR2  (celltype GENERIC)
      (view netlist (viewtype NETLIST)
        (interface
          (port I0 (direction INPUT))
          (port I1 (direction INPUT))
          (port O (direction OUTPUT))
        )
      )
    )
    (cell XOR2  (celltype GENERIC)
      (view netlist (viewtype NETLIST)
        (interface
          (port I0 (direction INPUT))
          (port I1 (direction INPUT))
          (port O (direction OUTPUT))
        )
      )
    )
    (cell OR3  (celltype GENERIC)
      (view netlist (viewtype NETLIST)
        (interface
          (port I0 (direction INPUT))
          (port I1 (direction INPUT))
          (port I2 (direction INPUT))
          (port O (direction OUTPUT))
        )
      )
    )
    (cell OR4  (celltype GENERIC)
      (view netlist (viewtype NETLIST)
        (interface
          (port I0 (direction INPUT))
          (port I1 (direction INPUT))
          (port I2 (direction INPUT))
          (port I3 (direction INPUT))
          (port O (direction OUTPUT))
        )
      )
    )
    (cell AND8  (celltype GENERIC)
      (view netlist (viewtype NETLIST)
        (interface
          (port I0 (direction INPUT))
          (port I1 (direction INPUT))
          (port I2 (direction INPUT))
          (port I3 (direction INPUT))
          (port I4 (direction INPUT))
          (port I5 (direction INPUT))
          (port I6 (direction INPUT))
          (port I7 (direction INPUT))
          (port O (direction OUTPUT))
        )
      )
    )
    (cell BUFE  (celltype GENERIC)
      (view netlist (viewtype NETLIST)
        (interface
          (port I (direction INPUT))
          (port E (direction INPUT))
          (port O (direction OUTPUT))
        )
      )
    )
    (cell GND  (celltype GENERIC)
      (view netlist (viewtype NETLIST)
        (interface
          (port G (direction OUTPUT))
        )
      )
    )
    (cell FD  (celltype GENERIC)
      (view netlist (viewtype NETLIST)
        (interface
          (port D (direction INPUT))
          (port C (direction INPUT))
          (port Q (direction OUTPUT))
        )
      )
    )
    (cell FDC  (celltype GENERIC)
      (view netlist (viewtype NETLIST)
        (interface
          (port D (direction INPUT))
          (port C (direction INPUT))
          (port CLR (direction INPUT))
          (port Q (direction OUTPUT))
        )
      )
    )
    (cell LD  (celltype GENERIC)
      (view netlist (viewtype NETLIST)
        (interface
          (port D (direction INPUT))
          (port G (direction INPUT))
          (port Q (direction OUTPUT))
        )
      )
    )
    (cell LPM_XOR3_1  (celltype GENERIC)
      (view netlist (viewtype NETLIST)
        (interface
          (port (rename Data_0 "Data<0>") (direction INPUT))
          (port (rename Data_1 "Data<1>") (direction INPUT))
          (port (rename Data_2 "Data<2>") (direction INPUT))
          (port Result (direction OUTPUT))
        )
        (contents
          (instance I_Result (viewref netlist (cellref XOR2 (libraryref DESIGNS))))
          (instance I_Xo0 (viewref netlist (cellref XOR2 (libraryref DESIGNS))))

          (net (rename Data_2 "Data<2>")  (joined
            (portref Data_2)
            (portref I1 (instanceref I_Result))
            )
          )
          (net Result  (joined
            (portref O (instanceref I_Result))
            (portref Result)
            )
          )
          (net (rename Data_1 "Data<1>")  (joined
            (portref Data_1)
            (portref I0 (instanceref I_Xo0))
            )
          )
          (net (rename Data_0 "Data<0>")  (joined
            (portref Data_0)
            (portref I1 (instanceref I_Xo0))
            )
          )
          (net N8  (joined
            (portref O (instanceref I_Xo0))
            (portref I0 (instanceref I_Result))
            )
          )
        )
      )
    )
    (cell LPM_ADD_SUB_1  (celltype GENERIC)
      (view netlist (viewtype NETLIST)
        (interface
          (port (rename DataA_0 "DataA<0>") (direction INPUT))
          (port (rename DataA_10 "DataA<10>") (direction INPUT))
          (port (rename DataA_11 "DataA<11>") (direction INPUT))
          (port (rename DataA_12 "DataA<12>") (direction INPUT))
          (port (rename DataA_13 "DataA<13>") (direction INPUT))
          (port (rename DataA_14 "DataA<14>") (direction INPUT))
          (port (rename DataA_15 "DataA<15>") (direction INPUT))
          (port (rename DataA_16 "DataA<16>") (direction INPUT))
          (port (rename DataA_17 "DataA<17>") (direction INPUT))
          (port (rename DataA_18 "DataA<18>") (direction INPUT))
          (port (rename DataA_19 "DataA<19>") (direction INPUT))
          (port (rename DataA_1 "DataA<1>") (direction INPUT))
          (port (rename DataA_20 "DataA<20>") (direction INPUT))
          (port (rename DataA_21 "DataA<21>") (direction INPUT))
          (port (rename DataA_22 "DataA<22>") (direction INPUT))
          (port (rename DataA_2 "DataA<2>") (direction INPUT))
          (port (rename DataA_3 "DataA<3>") (direction INPUT))
          (port (rename DataA_4 "DataA<4>") (direction INPUT))
          (port (rename DataA_5 "DataA<5>") (direction INPUT))
          (port (rename DataA_6 "DataA<6>") (direction INPUT))
          (port (rename DataA_7 "DataA<7>") (direction INPUT))
          (port (rename DataA_8 "DataA<8>") (direction INPUT))
          (port (rename DataA_9 "DataA<9>") (direction INPUT))