decode_man.vhd

xilinx reference design for 1553B BUS analyer using

	-- Purpose:  	Latch output data into buffers
	-- 
	CAPTURE: process(CLK16) 
	begin
		if CLK16'event and CLK16 = '1' then

			case main_curr_state is

	------------------------------------------------------------------------------------
			when IDLE =>			
			
				-- Reset message pointer
				sram_message_ptr <= SRAM_START_DATA ;


	------------------------------------------------------------------------------------
				when BETWEEN_WORDS =>

					man_word <= "0000000000000000" ;
					word_checksum <= "00" ;


	------------------------------------------------------------------------------------
				when PREAMBLE_CHECK =>

				if std_logic_vector(clock_count) = "101000" then	-- count to 40

					if (data1 = '1') or (data2 = '1') then
						-- Add in checksum and load bit for Data word
						-- Note checksum increment commented out due to 
						-- space problems with 256K CPLD.
						--word_checksum <= word_checksum + data1 ;
						man_word<= man_word(14 downto 0) & data1 ;

					end if ;

				end if ;


	------------------------------------------------------------------------------------
				when PREAMBLE_WAIT =>

				if std_logic_vector(pwclock_count) = "10100" then
					-- Add in checksum and load data bit for Command/Status word
					--word_checksum <= word_checksum + data3 ;
					man_word<= man_word(14 downto 0) & data3 ;

				end if ;

	------------------------------------------------------------------------------------
				when READ_DATA =>
											
				if (std_logic_vector(rclock_count(3 downto 0)) = "1100") then
					-- Add in checksum and load data bit
					--word_checksum <= word_checksum + data3 ;
					man_word<= man_word(14 downto 0) & data3 ;

				end if;

	------------------------------------------------------------------------------------
			when MESSAGE_COMPLETE =>
			
				-- Increment the SRAM message pointer
				sram_message_ptr <= sram_message_ptr + SRAM_INCREMENT ;


	------------------------------------------------------------------------------------
				when others =>
			
				
			end case ;  

		end if ;

	end process CAPTURE ;




	-- ************************ Process: MAIN_DECODE **************************
	-- Purpose:	Main high level state machine.  This state machine controls
	--		the execution of the Manchester decoding. 
	--
	MAIN_DECODE: process (main_curr_state)
	begin
	
		main_nxt_state <= main_curr_state ;
				
		statemachine_sram_enn <= '1' ;						
		statemachine_we <= '1' ;
		
		sram_address_com <= SM_ADDRESS ;				
		

		case main_curr_state is

			
			---------------------- IDLE State ---------------------------
			when IDLE =>			
			
				-- Set initial flag conditions
				
				main_nxt_state <= NEW_MESSAGE ;
				statemachine_oe <= '0' ;


			------------------- New Message State ------------------------
			when NEW_MESSAGE =>
			
				sram_address_com <= sram_message_ptr ;

				if sram_address_com > SRAM_END_DATA then
					main_nxt_state <= IDLE ;
				end if ;
				main_nxt_state <= BETWEEN_MESSAGES ;


			----------------- Between Messages State ----------------------
			when BETWEEN_MESSAGES =>
			
				-- If we have a 0 to 1 condition then start counting
				if mdi1 = '1' and mdi3 = '0' then	
					main_nxt_state <= TIME_TAG ;

					checksum_error <= '0' ;
					word_error <= '0' ;
					no_response <= '0' ;
					command_status <= "00" ; -- keep track of command/status words
					statemachine_oe <= '0';
					dout_type <= '0' ; -- Set word type to data

				else
					-- Else stay in this state
					main_nxt_state <= BETWEEN_MESSAGES ;

				end if;

			----------------- Between Messages State ----------------------
			when TIME_TAG =>

					main_nxt_state <= PREAMBLE_CHECK ;

					sram_address_com <= SM_ADDRESS + 2 ;
					-- Enable write to SRAM of time stamp
					statemachine_sram_enn <= '0' ;						
					statemachine_we <= '0' ;
					statemachine_oe <= '1';					
								
					MAN_DATA <= std_logic_vector(time_counter) ;


			------------------- Between Words State -----------------------
			when BETWEEN_WORDS =>

				-- If we have a 0 to 1 condition then start counting
				if mdi1 = '1' and mdi3 = '0' then	
					main_nxt_state <= PREAMBLE_CHECK ;

					checksum_error <= '0' ;
					word_error <= '0' ;
					statemachine_oe <= '0';
					data_word_count <= "00000" ;
					dout_type <= '0' ; -- Set word type to data

				-- Check for no response within a message (1553B max 12uS)
				-- if so, set the no response flag and go to NEW_MESSAGE
				elsif (std_logic_vector(rclock_count) = "11011111") then
					main_nxt_state <= MESSAGE_COMPLETE ;
					no_response <= '1' ;

				else
					-- Else stay in this state
					main_nxt_state <= BETWEEN_WORDS ;

				end if;


			------------------- Preamble Check State -----------------------
			when PREAMBLE_CHECK =>

				if std_logic_vector(clock_count) = "101000" then	-- count to 40

					if (data1 = '1') or (data2 = '1') then
						main_nxt_state <= READ_DATA;
						data_word_count <= data_word_count + "00001" ;
						command_status <= command_status + "01" ;

					else
						main_nxt_state <= PREAMBLE_WAIT;
					end if ;

				end if ;
	

			------------------- Preamble Wait State -----------------------
			when PREAMBLE_WAIT =>

				if std_logic_vector(pwclock_count) = "10111" then
					main_nxt_state <= READ_DATA ;

				end if ;
								
							
			------------------- Read Data State -----------------------
			when READ_DATA =>
											
				if (std_logic_vector(rclock_count(3 downto 0)) = "1100") then
					-- check if data1 and data2 are different, if not then word error

					if (data_error = '0') then
						word_error <= '1' ;
					end if ;

				end if;
				-- If at the end of the word, go to checksum state
				if (std_logic_vector(rclock_count(7 downto 0)) = "11101111") then
					main_nxt_state <= CHECKSUM ;
				end if ;

								
			-------------- Calculate Checksum and Verify ------------------
			when CHECKSUM =>
			
				if std_logic_vector(rclock_count(3 downto 0)) = "1100" then

					-- check if data3 and data4 are different, if not then word error
					if (data_error = '0') then
						word_error <= '1' ;
					end if ;
				end if;

				-- If at the end of the word, check checksum and go to OUTPUT state
				if (std_logic_vector(rclock_count(3 downto 0)) = "1111") then
					main_nxt_state <= OUTPUT ;
					-- Don't do checksum calculations in 256K CPLD
					--if (data3/= word_checksum(0)) then
						--checksum_error <= '1' ;
					--end if ;
				end if ;

			
			--------------------- Output State -----------------------
			when OUTPUT =>
			

				-- Write Data in MAN_DATA out at address sram_address_com

				sram_address_com <= SM_ADDRESS + 1 ;
								
				-- Enable write to SRAM
				statemachine_sram_enn <= '0' ;						
				statemachine_we <= '0' ;
				statemachine_oe <= '1';					
				MAN_DATA <= std_logic_vector(man_word) ;

				-- Check if we have a command and status word received
				-- otherwise, get the rest of this messages words.
				if std_logic_vector(command_status) = "10" then
					main_nxt_state <= MESSAGE_COMPLETE ;
				else
					main_nxt_state <= BETWEEN_WORDS ;
				end if ;
				

			------------------- Message Complete State --------------------
			when MESSAGE_COMPLETE =>
			

				-- Write out status word including word count, error flags,
			 	-- and upper timer bits.

				sram_address_com <= sram_message_ptr ;
								
				-- Enable write to SRAM
				statemachine_sram_enn <= '0' ;						
				statemachine_we <= '0' ;
				statemachine_oe <= '1';	
				
				--Note, the checksum, word error and word count data isn't used here
				-- due to space constraints in the 256K CPLD.  Re-enable in larger version.
				--MAN_DATA(7 downto 3) <= std_logic_vector(data_word_count(4 downto 0)) ;
				--MAN_DATA(2) <= checksum_error ;
				--MAN_DATA(1) <= word_error ;
				--MAN_DATA(0) <= no_response ;

				main_nxt_state <= NEW_MESSAGE ;
				

			------------------------ DEFAULT State -------------------------
			when others =>
			
				--main_nxt_state <= IDLE ;
				main_nxt_state <= BETWEEN_WORDS ;
				


		end case ;  


	end process MAIN_DECODE ;


end BEHAVE ;