decode_man.vhd

xilinx reference design for 1553B BUS analyer using

-- **************************************************************
--
-- File:  	decode_man.vhd
--
-- Purpose: 	Code to convert MIL-STD-1553 Manchester data to 
--					parallel 16 bit words and store into memory.
--	
--
-- **************************************************************


LIBRARY IEEE ;

USE ieee.STD_LOGIC_1164.all ;
USE ieee.STD_LOGIC_arith.all ;
USE ieee.STD_LOGIC_unsigned.all ;

entity DECODE_MAN is
	port(
	
		-- Miscellaneous Signals
		DIN_PRI				:	in	 STD_LOGIC ;
		DIN_SEC				:	in	 STD_LOGIC ;
		TEST_OUT				:	out STD_LOGIC ;
		CLK16					:	in	 STD_LOGIC ;
		MAN_DATA				:  out STD_LOGIC_vector(15 downto 0) ;
		reset_button		:  in  STD_LOGIC ;
		LED1_SEL				:	out STD_LOGIC ;
		LED2_SEL				:	out STD_LOGIC ;
		LED3_SEL				:	out STD_LOGIC ;
		RESET_COMMAND		:	in	 STD_LOGIC ;
		IO6					:	out STD_LOGIC ;
		IO7					:	out STD_LOGIC ;
		IO8					:	out STD_LOGIC ;
		IO9					:	out STD_LOGIC ;
		IO42					:	out STD_LOGIC ;
		IO44					:	out STD_LOGIC ;
		
		-- StateMachine Specific Signals
		Mux_Sel					:  out STD_LOGIC ;
		statemachine_sram_enn:  inout STD_LOGIC ;
		statemachine_we		:  inout STD_LOGIC ;
		statemachine_oe		:  inout STD_LOGIC ;
		SM_ADDRESS				:  inout STD_LOGIC_VECTOR(22 DOWNTO 0) ;
		SM_WE						:  out STD_LOGIC
	
	   ) ;

end DECODE_MAN ;

architecture BEHAVE of DECODE_MAN is

-- ************************* CONSTANT DECLARATIONS *******************************	
	
-- *********************** SRAM Constants for Messages ***************************

constant SRAM_START_DATA 	: STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000000000" ;
constant SRAM_INCREMENT		: STD_LOGIC_VECTOR (22 downto 0) :=  "00000000000000000100100" ;
constant SRAM_END_DATA   	: STD_LOGIC_VECTOR (22 downto 0) := "00001111001100101110100" ;

-- ************************ SIGNAL DECLARATIONS *********************************

-- Main State Machine State Type
type Main_StateType is ( IDLE, NEW_MESSAGE, BETWEEN_MESSAGES, TIME_TAG, BETWEEN_WORDS, 
	PREAMBLE_CHECK, PREAMBLE_WAIT, READ_DATA, CHECKSUM, OUTPUT, MESSAGE_COMPLETE) ;

-- Synchronous state machine state identifiers
signal 	main_curr_state, main_nxt_state   : Main_StateType ;

-- Manchester Decode Variables
signal 	time_counter 	: unsigned (15 downto 0) ; -- Counter for time tagging
signal	clock_count		: unsigned (5 downto 0) ;  -- Counter for message timing
signal	pwclock_count	: unsigned (4 downto 0) ;  -- Counter for message timing
signal	rclock_count	: unsigned (7 downto 0) ;  -- Counter for message timing
signal	word_checksum	: unsigned (1 downto 0) ;
signal	command_status	: unsigned (1 downto 0) ;
signal	data_word_count: unsigned (4 downto 0) ;  -- Counter # of data words
signal	man_word			: unsigned (15 downto 0) ;
signal	nrz 				: std_logic ;
signal	dout_type 		: std_logic ;
signal	data1				: std_logic ;
signal	data2				: std_logic ;
signal	data3				: std_logic ;
signal	data4				: std_logic ;

signal	mdi1				: std_logic ;
signal	mdi2				: std_logic ;
signal	mdi3				: std_logic ;
signal   data_error		: std_logic ;

signal	checksum_error : std_logic ;
signal	word_error 		: std_logic ;
signal	no_response		: std_logic ;

-- SRAM address output for writing incoming data to memory
signal 	sram_address_com : STD_LOGIC_VECTOR (22 downto 0) ;
signal 	sram_message_ptr : STD_LOGIC_VECTOR (22 downto 0) ;


begin 

	-- *************************** SIGNAL DEFINITIONS **************************

	-- Data is only put out to the SRAM when in these three states.					
	with main_curr_state select SM_WE <= '1' when OUTPUT, '1' when TIME_TAG, 
			'1' when MESSAGE_COMPLETE, '0' when others ;	
	with main_curr_state select Mux_Sel <= '1' when OUTPUT, '1' when TIME_TAG,
 			'1' when MESSAGE_COMPLETE, '0' when others ;


	-- Manchester data errors are defined as  
	-- not having a 0 to 1 or 1 to 0 transition.
	data_error <= data3 xor data4 ;

	-- DEBUG code
	--with main_curr_state select IO8 <= '1' when BETWEEN_MESSAGES, '0' when others ;
	--with main_curr_state select IO9 <= '1' when MESSAGE_COMPLETE, '0' when others ;

	-- ***************************** Process: SEQ *********************************
	-- Purpose:  	Synchronize target state machine
	-- 
	SEQ: process(CLK16, reset_button, RESET_COMMAND) 
	begin
	
		if (reset_button = '0') then
			main_curr_state <= IDLE ;
			--main_curr_state <= BETWEEN_WORDS ;

		elsif RESET_COMMAND = '1' then
			main_curr_state <= IDLE ;
						
			-- Initialize sm_address
			SM_ADDRESS <= (others => '0') ;

		elsif CLK16'event and CLK16 = '1' then

			main_curr_state <= main_nxt_state ;

			-- Keep current data and last data
			mdi3 <= mdi2;
			mdi1 <= DIN_PRI ;
			
			-- Register output sm_address value
			SM_ADDRESS <= sram_address_com ;
			time_counter <= time_counter + "0000000000000001" ;
		end if ;
					
	end process SEQ ;


	-- ***************************** Process: LAST *********************************
	-- Purpose:  	Hold the previous data value in the input manchester signal
	-- 
	LAST: process(CLK16) 
	begin
		if CLK16'event and CLK16 = '0' then

			mdi2 <= mdi1 ;

		end if ;
	end process LAST ;


	-- ***************************** Process: TIMERS *********************************
	-- Purpose:  	Control counters for state timing
	-- 
	TIMERS: process(CLK16) 
	begin
		if CLK16'event and CLK16 = '0' then

			case main_curr_state is

	-----------------------------------------------------------------------------------
				when IDLE =>			
			
					clock_count <= "000000" ;
					pwclock_count <= "00000" ;
					rclock_count <= "00000000" ;

	------------------------------------------------------------------------------------
				when BETWEEN_MESSAGES =>

					clock_count <= "000000" ;
					pwclock_count <= "00000" ;

	------------------------------------------------------------------------------------
				when TIME_TAG =>
					clock_count <= clock_count + "000001" ;

	------------------------------------------------------------------------------------
				when BETWEEN_WORDS =>

					clock_count <= "000000" ;
					pwclock_count <= "00000" ;
					rclock_count <= rclock_count + "00000001" ;

	------------------------------------------------------------------------------------
				when PREAMBLE_CHECK =>

					clock_count <= clock_count + "000001" ;
					rclock_count <= "00000000" ;

	------------------------------------------------------------------------------------
				when PREAMBLE_WAIT =>

					pwclock_count <= pwclock_count + "00001" ;
								
	------------------------------------------------------------------------------------
				when READ_DATA =>
											
					rclock_count <= rclock_count + "00000001" ;

	------------------------------------------------------------------------------------
				when CHECKSUM =>

					rclock_count <= rclock_count + "00000001" ;
			
	------------------------------------------------------------------------------------
				when OUTPUT =>

					rclock_count <= "00000000" ;

	------------------------------------------------------------------------------------
				when others =>
			
				
			end case ;  

		end if ;

	end process TIMERS ;


	-- ***************************** Process: DATA ****************************
	-- Purpose:  	Latch data during process reads
	-- 
	DATA: process(CLK16) 
	begin
		if CLK16'event and CLK16 = '1' then

			case main_curr_state is

	------------------------------------------------------------------------------------
				when PREAMBLE_CHECK =>

					if (std_logic_vector(clock_count) = "011011") then					
						-- if we have a 1, then this is a data word.
						data1 <= mdi1 ;	-- This is a Data word so set the first bit to 1
					end if ;

					if std_logic_vector(clock_count) = "100011" then	-- count to 35

						data2 <= mdi1 ;	-- This is a Data word so set the first bit to 1
					end if ;

	------------------------------------------------------------------------------------
				when PREAMBLE_WAIT =>

					if std_logic_vector(pwclock_count) = "01011" then
						data3 <= mdi1 ; -- Check first data point and latch
					end if ;

					if std_logic_vector(pwclock_count) = "10100" then
						data4 <= mdi1 ; -- Check second data point and latch
 			   	end if ;

	------------------------------------------------------------------------------------
				when READ_DATA =>
											
					-- If 1/4 of the way through the manchester bit, get data
					if (std_logic_vector(rclock_count(3 downto 0)) = "0011") then
						data3 <= mdi1 ;
					end if ;

					-- If 3/4 of the way through the manchester bit, get data
					if (std_logic_vector(rclock_count(3 downto 0)) = "1100") then
						data4 <= mdi1 ;
					end if ;

	------------------------------------------------------------------------------------
				when CHECKSUM =>
			
					-- If 1/4 of the way through the manchester bit, get data
					if std_logic_vector(rclock_count(3 downto 0)) = "0011" then
						data3 <= mdi1 ;
					end if;

					-- If 3/4 of the way through the manchester bit, get data
					if std_logic_vector(rclock_count(3 downto 0)) = "1100" then
						data4 <= mdi1 ;
					end if ;

	------------------------------------------------------------------------------------
				when others =>
			
				
			end case ;  

		end if ;

	end process DATA ;



	-- **************************** Process: CAPTURE *************************