📄 top_level.ph0
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dvm_rclock_count_1 node istype 'reg, collapse'; " 1 pt.
dvm_rclock_count_2 node istype 'reg, collapse'; " 1 pt.
dvm_rclock_count_3 node istype 'reg, collapse'; " 1 pt.
dvm_rclock_count_4 node istype 'reg, collapse'; " 1 pt.
dvm_rclock_count_5 node istype 'reg, collapse'; " 1 pt.
dvm_rclock_count_6 node istype 'reg, collapse'; " 1 pt.
dvm_rclock_count_7 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_0 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_1 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_10 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_11 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_12 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_13 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_14 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_15 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_16 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_17 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_18 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_19 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_2 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_20 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_21 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_22 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_3 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_4 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_5 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_6 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_7 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_8 node istype 'reg, collapse'; " 1 pt.
dvm_sram_message_ptr_9 node istype 'reg, collapse'; " 1 pt.
dvm_time_counter_0 node istype 'reg, collapse'; " 1 pt.
dvm_time_counter_1 node istype 'reg, collapse'; " 1 pt.
dvm_time_counter_10 node istype 'reg, collapse'; " 1 pt.
dvm_time_counter_11 node istype 'reg, collapse'; " 1 pt.
dvm_time_counter_12 node istype 'reg, collapse'; " 1 pt.
dvm_time_counter_13 node istype 'reg, collapse'; " 1 pt.
dvm_time_counter_14 node istype 'reg, collapse'; " 1 pt.
dvm_time_counter_15 node istype 'reg, collapse'; " 1 pt.
dvm_time_counter_2 node istype 'reg, collapse'; " 1 pt.
dvm_time_counter_3 node istype 'reg, collapse'; " 1 pt.
dvm_time_counter_4 node istype 'reg, collapse'; " 1 pt.
dvm_time_counter_5 node istype 'reg, collapse'; " 1 pt.
dvm_time_counter_6 node istype 'reg, collapse'; " 1 pt.
dvm_time_counter_7 node istype 'reg, collapse'; " 1 pt.
dvm_time_counter_8 node istype 'reg, collapse'; " 1 pt.
dvm_time_counter_9 node istype 'reg, collapse'; " 1 pt.
EQUATIONS
LPM_ADD_SUB_1/N100 = dvm_sram_message_ptr_12.Q & LPM_ADD_SUB_1/N93
; "--- [PT=1, FI=2, LVL=10] ---
LPM_ADD_SUB_1/N107 = dvm_sram_message_ptr_13.Q & LPM_ADD_SUB_1/N100
; "--- [PT=1, FI=2, LVL=11] ---
LPM_ADD_SUB_1/N114 = dvm_sram_message_ptr_14.Q & LPM_ADD_SUB_1/N107
; "--- [PT=1, FI=2, LVL=12] ---
LPM_ADD_SUB_1/N121 = dvm_sram_message_ptr_15.Q & LPM_ADD_SUB_1/N114
; "--- [PT=1, FI=2, LVL=13] ---
LPM_ADD_SUB_1/N128 = dvm_sram_message_ptr_16.Q & LPM_ADD_SUB_1/N121
; "--- [PT=1, FI=2, LVL=14] ---
LPM_ADD_SUB_1/N135 = dvm_sram_message_ptr_17.Q & LPM_ADD_SUB_1/N128
; "--- [PT=1, FI=2, LVL=15] ---
LPM_ADD_SUB_1/N142 = dvm_sram_message_ptr_18.Q & LPM_ADD_SUB_1/N135
; "--- [PT=1, FI=2, LVL=16] ---
LPM_ADD_SUB_1/N150 = dvm_sram_message_ptr_19.Q & LPM_ADD_SUB_1/N142
; "--- [PT=1, FI=2, LVL=17] ---
LPM_ADD_SUB_1/N157 = dvm_sram_message_ptr_20.Q & LPM_ADD_SUB_1/N150
; "--- [PT=1, FI=2, LVL=18] ---
LPM_ADD_SUB_1/N164 = dvm_sram_message_ptr_21.Q & LPM_ADD_SUB_1/N157
; "--- [PT=1, FI=2, LVL=19] ---
LPM_ADD_SUB_1/N175 = dvm_sram_message_ptr_5.Q & LPM_ADD_SUB_1/N59
; "--- [PT=1, FI=2, LVL=3] ---
! LPM_ADD_SUB_1/N179 = !dvm_sram_message_ptr_5.Q & !LPM_ADD_SUB_1/N59
; "--- [PT=1, FI=2, LVL=3] ---
! LPM_ADD_SUB_1/N181 = LPM_ADD_SUB_1/N179; "--- [PT=1, FI=1, LVL=4] ---
LPM_ADD_SUB_1/N55 = dvm_sram_message_ptr_3.Q & dvm_sram_message_ptr_2.Q
; "--- [PT=1, FI=2, LVL=1] ---
LPM_ADD_SUB_1/N59 = dvm_sram_message_ptr_4.Q & LPM_ADD_SUB_1/N55
; "--- [PT=1, FI=2, LVL=2] ---
! LPM_ADD_SUB_1/N63 = !dvm_sram_message_ptr_5.Q & !LPM_ADD_SUB_1/N59
; "--- [PT=1, FI=2, LVL=3] ---
LPM_ADD_SUB_1/N67 = dvm_sram_message_ptr_6.Q & LPM_ADD_SUB_1/N63
; "--- [PT=1, FI=2, LVL=4] ---
LPM_ADD_SUB_1/N71 = dvm_sram_message_ptr_7.Q & LPM_ADD_SUB_1/N67
; "--- [PT=1, FI=2, LVL=5] ---
LPM_ADD_SUB_1/N75 = dvm_sram_message_ptr_8.Q & LPM_ADD_SUB_1/N71
; "--- [PT=1, FI=2, LVL=6] ---
LPM_ADD_SUB_1/N79 = dvm_sram_message_ptr_9.Q & LPM_ADD_SUB_1/N75
; "--- [PT=1, FI=2, LVL=7] ---
LPM_ADD_SUB_1/N86 = dvm_sram_message_ptr_10.Q & LPM_ADD_SUB_1/N79
; "--- [PT=1, FI=2, LVL=8] ---
LPM_ADD_SUB_1/N93 = dvm_sram_message_ptr_11.Q & LPM_ADD_SUB_1/N86
; "--- [PT=1, FI=2, LVL=9] ---
LPM_ADD_SUB_1/Result_0 = dvm_sram_message_ptr_0.Q
; "--- [PT=1, FI=1, LVL=1] ---
LPM_ADD_SUB_1/Result_1 = dvm_sram_message_ptr_1.Q
; "--- [PT=1, FI=1, LVL=1] ---
LPM_XOR3_1/N8 = N833 & !N2283
# !N833 & N2283; "--- [PT=2, FI=2, LVL=5] ---
N1002 = dvm_I_sm_address_3.Q & N855; "--- [PT=1, FI=2, LVL=6] ---
N1007 = sp_a[5] & N733; "--- [PT=1, FI=2, LVL=7] ---
N1011 = dvm_I_sm_address_4.Q & N855; "--- [PT=1, FI=2, LVL=6] ---
N1016 = sp_a[6] & N733; "--- [PT=1, FI=2, LVL=7] ---
N1020 = dvm_I_sm_address_5.Q & N855; "--- [PT=1, FI=2, LVL=6] ---
N1025 = sp_a[7] & N733; "--- [PT=1, FI=2, LVL=7] ---
N1029 = dvm_I_sm_address_6.Q & N855; "--- [PT=1, FI=2, LVL=6] ---
N1034 = sp_a[8] & N733; "--- [PT=1, FI=2, LVL=7] ---
N1038 = dvm_I_sm_address_7.Q & N855; "--- [PT=1, FI=2, LVL=6] ---
N1043 = sp_a[9] & N733; "--- [PT=1, FI=2, LVL=7] ---
N1047 = dvm_I_sm_address_8.Q & N855; "--- [PT=1, FI=2, LVL=6] ---
N1052 = sp_a[10] & N733; "--- [PT=1, FI=2, LVL=7] ---
N1056 = dvm_I_sm_address_9.Q & N855; "--- [PT=1, FI=2, LVL=6] ---
! N1077 = !N488 & !led0_sel.COM; "--- [PT=1, FI=2, LVL=2] ---
N1080 = reset_button & led0_sel.COM; "--- [PT=1, FI=2, LVL=1] ---
N1083 = reset_button & N491; "--- [PT=1, FI=2, LVL=2] ---
N1088 = dvm_main_curr_state_FFD2.Q & dvm_main_curr_state_FFD4.Q &
dvm_main_curr_state_FFD1.Q & dvm_main_curr_state_FFD3.Q
; "--- [PT=1, FI=4, LVL=1] ---
! N1092 = !N1088 & !N833 & !N494; "--- [PT=1, FI=3, LVL=3] ---
! N1094 = N1092; "--- [PT=1, FI=1, LVL=4] ---
N1100 = dvm_main_curr_state_FFD1.Q & dvm_main_curr_state_FFD3.Q &
dvm_main_curr_state_FFD2.Q & N599; "--- [PT=1, FI=4, LVL=2] ---
! N1106 = !dvm_main_curr_state_FFD1.Q & !dvm_main_curr_state_FFD3.Q & !
dvm_main_curr_state_FFD4.Q & !dvm_main_curr_state_FFD2.Q
; "--- [PT=1, FI=4, LVL=1] ---
! N1108 = N1106; "--- [PT=1, FI=1, LVL=2] ---
N1114 = dvm_main_curr_state_FFD1.Q & dvm_main_curr_state_FFD2.Q & N710 & N599
; "--- [PT=1, FI=4, LVL=2] ---
! N1116 = !N1100 & !N1114 & !N1108; "--- [PT=1, FI=3, LVL=3] ---
! N1118 = N1116; "--- [PT=1, FI=1, LVL=4] ---
N1120 = N1118 & N1094; "--- [PT=1, FI=2, LVL=5] ---
! N1125 = !N1088 & !N833; "--- [PT=1, FI=2, LVL=3] ---
N1127 = N1125 & N494; "--- [PT=1, FI=2, LVL=4] ---
! N1129 = !N1127 & !N1120; "--- [PT=1, FI=2, LVL=6] ---
! N1133 = !N833 & !N749 & !N1088; "--- [PT=1, FI=3, LVL=6] ---
! N1135 = N1133; "--- [PT=1, FI=1, LVL=7] ---
N1139 = dvm_clock_count_1.Q & N1135; "--- [PT=1, FI=2, LVL=8] ---
N1144 = dvm_clock_count_0.Q & !dvm_clock_count_1.Q
# !dvm_clock_count_0.Q & dvm_clock_count_1.Q
; "--- [PT=2, FI=2, LVL=1] ---
N1146 = N1144 & N735; "--- [PT=1, FI=2, LVL=6] ---
! N1148 = !N1146 & !N1139; "--- [PT=1, FI=2, LVL=9] ---
N1151 = dvm_clock_count_2.Q & N1135; "--- [PT=1, FI=2, LVL=8] ---
N1157 = dvm_clock_count_0.Q & dvm_clock_count_1.Q & N509
; "--- [PT=1, FI=3, LVL=2] ---
N1161 = dvm_clock_count_0.Q & dvm_clock_count_1.Q
; "--- [PT=1, FI=2, LVL=1] ---
! N1163 = N1161; "--- [PT=1, FI=1, LVL=2] ---
N1166 = dvm_clock_count_2.Q & N1163; "--- [PT=1, FI=2, LVL=3] ---
! N1168 = !N1166 & !N1157; "--- [PT=1, FI=2, LVL=4] ---
N1170 = N1168 & N735; "--- [PT=1, FI=2, LVL=6] ---
! N1172 = !N1170 & !N1151; "--- [PT=1, FI=2, LVL=9] ---
N1176 = dvm_clock_count_3.Q & N1135; "--- [PT=1, FI=2, LVL=8] ---
N1182 = dvm_clock_count_2.Q & dvm_clock_count_0.Q & dvm_clock_count_1.Q
; "--- [PT=1, FI=3, LVL=1] ---
N1185 = N1182 & !dvm_clock_count_3.Q
# !N1182 & dvm_clock_count_3.Q; "--- [PT=2, FI=2, LVL=2] ---
N1187 = N1185 & N735; "--- [PT=1, FI=2, LVL=6] ---
! N1189 = !N1187 & !N1176; "--- [PT=1, FI=2, LVL=9] ---
N1193 = dvm_clock_count_4.Q & N1135; "--- [PT=1, FI=2, LVL=8] ---
N1200 = dvm_clock_count_3.Q & dvm_clock_count_2.Q & dvm_clock_count_0.Q &
dvm_clock_count_1.Q; "--- [PT=1, FI=4, LVL=1] ---
N1203 = N1200 & !dvm_clock_count_4.Q
# !N1200 & dvm_clock_count_4.Q; "--- [PT=2, FI=2, LVL=2] ---
N1205 = N1203 & N735; "--- [PT=1, FI=2, LVL=6] ---
! N1207 = !N1205 & !N1193; "--- [PT=1, FI=2, LVL=9] ---
N1210 = dvm_clock_count_5.Q & N1135; "--- [PT=1, FI=2, LVL=8] ---
N1215 = dvm_clock_count_4.Q & N1200; "--- [PT=1, FI=2, LVL=2] ---
! N1217 = N1215; "--- [PT=1, FI=1, LVL=3] ---
N1220 = dvm_clock_count_5.Q & N1217; "--- [PT=1, FI=2, LVL=4] ---
N1225 = dvm_clock_count_4.Q & N497 & N1200; "--- [PT=1, FI=3, LVL=2] ---
! N1227 = !N1225 & !N1220; "--- [PT=1, FI=2, LVL=5] ---
N1229 = N1227 & N735; "--- [PT=1, FI=2, LVL=6] ---
! N1231 = !N1229 & !N1210; "--- [PT=1, FI=2, LVL=9] ---
N1239 = dvm_main_curr_state_FFD3.Q & dvm_main_curr_state_FFD2.Q & N713 & N599
; "--- [PT=1, FI=4, LVL=2] ---
! N1241 = !N1100 & !N1114 & !N1239 & !N1108; "--- [PT=1, FI=4, LVL=3] ---
! N1243 = N1241; "--- [PT=1, FI=1, LVL=4] ---
N1246 = dvm_pwclock_count_0.Q & N1243; "--- [PT=1, FI=2, LVL=5] ---
N1250 = N1239 & N500; "--- [PT=1, FI=2, LVL=3] ---
! N1252 = !N1250 & !N1246; "--- [PT=1, FI=2, LVL=6] ---
N1256 = dvm_pwclock_count_1.Q & N1243; "--- [PT=1, FI=2, LVL=5] ---
N1261 = dvm_pwclock_count_1.Q & !dvm_pwclock_count_0.Q
# !dvm_pwclock_count_1.Q & dvm_pwclock_count_0.Q
; "--- [PT=2, FI=2, LVL=1] ---
N1263 = N1261 & N1239; "--- [PT=1, FI=2, LVL=3] ---
! N1265 = !N1263 & !N1256; "--- [PT=1, FI=2, LVL=6] ---
N1268 = dvm_pwclock_count_2.Q & N1243; "--- [PT=1, FI=2, LVL=5] ---
N1272 = dvm_pwclock_count_0.Q & dvm_pwclock_count_1.Q
; "--- [PT=1, FI=2, LVL=1] ---
N1275 = N1272 & !dvm_pwclock_count_2.Q
# !N1272 & dvm_pwclock_count_2.Q; "--- [PT=2, FI=2, LVL=2] ---
N1278 = N1239 & N1275; "--- [PT=1, FI=2, LVL=3] ---
! N1280 = !N1278 & !N1268; "--- [PT=1, FI=2, LVL=6] ---
N1283 = dvm_pwclock_count_3.Q & N1243; "--- [PT=1, FI=2, LVL=5] ---
N1289 = dvm_pwclock_count_2.Q & dvm_pwclock_count_0.Q & dvm_pwclock_count_1.Q
; "--- [PT=1, FI=3, LVL=1] ---
N1291 = dvm_pwclock_count_3.Q & !N1289
# !dvm_pwclock_count_3.Q & N1289; "--- [PT=2, FI=2, LVL=2] ---
N1294 = N1239 & N1291; "--- [PT=1, FI=2, LVL=3] ---
! N1296 = !N1294 & !N1283; "--- [PT=1, FI=2, LVL=6] ---
N1299 = dvm_pwclock_count_4.Q & N1243; "--- [PT=1, FI=2, LVL=5] ---
N1303 = dvm_pwclock_count_3.Q & N1289; "--- [PT=1, FI=2, LVL=2] ---
! N1305 = N1303; "--- [PT=1, FI=1, LVL=3] ---
N1308 = dvm_pwclock_count_4.Q & N1305; "--- [PT=1, FI=2, LVL=4] ---
N1313 = dvm_pwclock_count_3.Q & N503 & N1289; "--- [PT=1, FI=3, LVL=2] ---
! N1315 = !N1313 & !N1308; "--- [PT=1, FI=2, LVL=5] ---
N1318 = N1239 & N1315; "--- [PT=1, FI=2, LVL=6] ---
! N1320 = !N1318 & !N1299; "--- [PT=1, FI=2, LVL=7] ---
! N1324 = !N1108 & !N849 & !N1088; "--- [PT=1, FI=3, LVL=4] ---
! N1326 = N1324; "--- [PT=1, FI=1, LVL=5] ---
! N1332 = !dvm_main_curr_state_FFD1.Q & !dvm_main_curr_state_FFD3.Q & !N581 & !
dvm_main_curr_state_FFD4.Q; "--- [PT=1, FI=4, LVL=2] ---
! N1334 = N1332; "--- [PT=1, FI=1, LVL=3] ---
! N1340 = !dvm_main_curr_state_FFD1.Q & !dvm_main_curr_state_FFD3.Q & !N581
; "--- [PT=1, FI=3, LVL=2] ---
! N1342 = N1340; "--- [PT=1, FI=1, LVL=3] ---
N1345 = dvm_main_curr_state_FFD4.Q & N1342; "--- [PT=1, FI=2, LVL=4] ---
! N1347 = !N1334 & !N1345 & !N1114; "--- [PT=1, FI=3, LVL=5] ---
! N1349 = N1347; "--- [PT=1, FI=1, LVL=6] ---
N1351 = N1349 & N1326; "--- [PT=1, FI=2, LVL=7] ---
N1354 = dvm_rclock_count_0.Q & N1351; "--- [PT=1, FI=2, LVL=8] ---
! N1358 = !dvm_rclock_count_0.Q & !N1349; "--- [PT=1, FI=2, LVL=7] ---
! N1360 = N1358; "--- [PT=1, FI=1, LVL=8] ---
! N1362 = !N1360 & !N1354; "--- [PT=1, FI=2, LVL=9] ---
N1365 = dvm_rclock_count_1.Q & N1351; "--- [PT=1, FI=2, LVL=8] ---
N1370 = dvm_rclock_count_0.Q & !dvm_rclock_count_1.Q
# !dvm_rclock_count_0.Q & dvm_rclock_count_1.Q
; "--- [PT=2, FI=2, LVL=1] ---
N1372 = N1370 & N737; "--- [PT=1, FI=2, LVL=8] ---
! N1374 = !N1372 & !N1365; "--- [PT=1, FI=2, LVL=9] ---
N1377 = dvm_rclock_count_2.Q & N1351; "--- [PT=1, FI=2, LVL=8] ---
N1383 = dvm_rclock_count_0.Q & dvm_rclock_count_1.Q
; "--- [PT=1, FI=2, LVL=1] ---
N1385 = dvm_rclock_count_2.Q & !N1383
# !dvm_rclock_count_2.Q & N1383; "--- [PT=2, FI=2, LVL=2] ---
N1387 = N1385 & N737; "--- [PT=1, FI=2, LVL=8] ---
! N1389 = !N1387 & !N1377; "--- [PT=1, FI=2, LVL=9] ---
N1392 = dvm_rclock_count_3.Q & N1351; "--- [PT=1, FI=2, LVL=8] ---
N1398 = dvm_rclock_count_2.Q & dvm_rclock_count_0.Q & dvm_rclock_count_1.Q
; "--- [PT=1, FI=3, LVL=1] ---
N1401 = N1398 & !dvm_rclock_count_3.Q
# !N1398 & dvm_rclock_count_3.Q; "--- [PT=2, FI=2, LVL=2] ---
N1403 = N1401 & N737; "--- [PT=1, FI=2, LVL=8] ---
! N1405 = !N1403 & !N1392; "--- [PT=1, FI=2, LVL=9] ---
N1408 = dvm_rclock_count_4.Q & N1351; "--- [PT=1, FI=2, LVL=8] ---
N1415 = dvm_rclock_count_3.Q & dvm_rclock_count_2.Q & dvm_rclock_count_0.Q &
dvm_rclock_count_1.Q; "--- [PT=1, FI=4, LVL=1] ---
N1418 = N1415 & !dvm_rclock_count_4.Q
# !N1415 & dvm_rclock_count_4.Q; "--- [PT=2, FI=2, LVL=2] ---
N1420 = N1418 & N737; "--- [PT=1, FI=2, LVL=8] ---
! N1422 = !N1420 & !N1408; "--- [PT=1, FI=2, LVL=9] ---
N1425 = dvm_rclock_count_5.Q & N1351; "--- [PT=1, FI=2, LVL=8] ---
N1430 = dvm_rclock_count_4.Q & N1415; "--- [PT=1, FI=2, LVL=2] ---
N1433 = N1430 & !dvm_rclock_count_5.Q
# !N1430 & dvm_rclock_count_5.Q; "--- [PT=2, FI=2, LVL=3] ---
N1435 = N1433 & N737; "--- [PT=1, FI=2, LVL=8] ---
! N1437 = !N1435 & !N1425; "--- [PT=1, FI=2, LVL=9] ---
N1441 = dvm_rclock_count_6.Q & N1351; "--- [PT=1, FI=2, LVL=8] ---
N1447 = dvm_rclock_count_5.Q & dvm_rclock_count_4.Q & N1415
; "--- [PT=1, FI=3, LVL=2] ---
N1450 = N1447 & !dvm_rclock_count_6.Q
# !N1447 & dvm_rclock_count_6.Q; "--- [PT=2, FI=2, LVL=3] ---
N1452 = N1450 & N737; "--- [PT=1, FI=2, LVL=8] ---
! N1454 = !N1452 & !N1441; "--- [PT=1, FI=2, LVL=9] ---
N1457 = dvm_rclock_count_7.Q & N1351; "--- [PT=1, FI=2, LVL=8] ---
N1462 = dvm_rclock_count_6.Q & N1447; "--- [PT=1, FI=2, LVL=3] ---
! N1464 = N1462; "--- [PT=1, FI=1, LVL=4] ---
N1467 = dvm_rclock_count_7.Q & N1464; "--- [PT=1, FI=2, LVL=5] ---
N1472 = dvm_rclock_count_6.Q & N506 & N1447; "--- [PT=1, FI=3, LVL=3] ---
! N1474 = !N1472 & !N1467; "--- [PT=1, FI=2, LVL=6] ---
N1476 = N1474 & N737; "--- [PT=1, FI=2, LVL=8] ---
! N1478 = !N1476 & !N1457; "--- [PT=1, FI=2, LVL=9] ---
N1482 = dvm_clock_count_4.Q & dvm_clock_count_3.Q & N497
; "--- [PT=1, FI=3, LVL=2] ---
N1488 = dvm_clock_count_0.Q & dvm_clock_count_1.Q & N509
; "--- [PT=1, FI=3, LVL=2] ---
N1490 = N1088 & N1482 & N1488; "--- [PT=1, FI=3, LVL=3] ---
! N1494 = !dvm_clock_count_3.Q & !dvm_clock_count_4.Q & !N497
; "--- [PT=1, FI=3, LVL=2] ---
! N1496 = N1494; "--- [PT=1, FI=1, LVL=3] ---
N1500 = N1157 & N1496 & N1088; "--- [PT=1, FI=3, LVL=4] ---
N1504 = dvm_main_curr_state_FFD4.Q & N1342; "--- [PT=1, FI=2, LVL=4] ---
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