top_level.vhd

xilinx reference design for 1553B BUS analyer using

-- **************************************************************
-- File:  		top_level.vhd
--
-- Purpose:  		This top level file creates the bidirectional buffering
--           		scheme in the XPLA3.  It instantiates the state machine 
--						which receives serial Manchester MIL-STD-1553 Data.  
--
-- Modified:       		8/13/01
--
-- Version: 1.0
--
--	Initial Release of the program 
--
-- **************************************************************

library IEEE ;
use IEEE.STD_LOGIC_1164.all ;
use IEEE.STD_LOGIC_arith.all ;

entity TOP_LEVEL is
	port(
	SP_CS0n	 		: in 	STD_LOGIC ;
	SP_CS1n   		: in 	STD_LOGIC ;
	SP_WEn  			: in 	STD_LOGIC ;
	SP_OEn			: in 	STD_LOGIC ;
	SP_D				: inout STD_LOGIC_VECTOR(15 DOWNTO 0) ;
	SP_A				: in 	STD_LOGIC_VECTOR(23 DOWNTO 1) ;
	SP_A_0 			: out   STD_LOGIC ;

	A						: out 	STD_LOGIC_VECTOR(22 DOWNTO 0) ;
	D						: inout  STD_LOGIC_VECTOR(15 DOWNTO 0) ;
	FLASH_CS0n			: out 	STD_LOGIC ;
	FLASH_WR_PROTECT	: out 	STD_LOGIC ;
	SRAM_CS1n			: inout  STD_LOGIC ;
	OEn					: out 	STD_LOGIC ;
	RWn					: out 	STD_LOGIC ;

	DIN_PRI				: in		STD_LOGIC ;	-- 1553 serial data in Primary
	DIN_SEC				: in		STD_LOGIC ;	-- 1553 serial data in Secondary
	TEST_OUT				: out		STD_LOGIC ;  -- Data Out for Debug
	CLK16					: in		STD_LOGIC ;	-- 16MHz clock input
	IO7					: out		STD_LOGIC ;
	IO8					: out		STD_LOGIC ;
	IO9					: out		STD_LOGIC ;
	IO6					: out 	STD_LOGIC ;	-- Data Out for Debug
	IO42					: out 	STD_LOGIC ;	-- Data Out for Debug
	IO44					: out 	STD_LOGIC ;	-- Data Out for Debug
	reset_button		: in		STD_LOGIC ;	-- reset hardware

	SRAM_UPPER_BYTEn	: out 	STD_LOGIC ;
	SRAM_LOW_BYTEn		: out 	STD_LOGIC ;
	RESET_MEMn			: out 	STD_LOGIC ;
	
	LED0_SEL				: out 	STD_LOGIC ;
	LED1_SEL				: out 	STD_LOGIC ;
	LED2_SEL				: out 	STD_LOGIC ;
	LED3_SEL				: out 	STD_LOGIC

	) ;

end TOP_LEVEL ;

architecture BEHAVE of TOP_LEVEL is

-- Reset Address is the address location for the contol of data capture
-- A1 to A5 asserted 
constant RESET_ADDR : STD_LOGIC_VECTOR(23 downto 0) := "000001111111111111111110" ;  
--constant RESET_ADDR : STD_LOGIC_VECTOR(23 downto 0) := "000000000000000000000010" ;  


-- ************************ SIGNAL DECLARATIONS *****************
signal SM_WE						: STD_LOGIC ;

signal SRAM_Write_En 			: STD_LOGIC ;
signal SRAM_Read_En 				: STD_LOGIC ;
signal SRAM_ReADDATA				: STD_LOGIC_VECTOR(15 DOWNTO 0) ;
signal SRAM_Write_Data			: STD_LOGIC_VECTOR(15 DOWNTO 0) ;
	
signal StateMachine_SRAM_ENn	: STD_LOGIC ;
signal StateMachine_WE			: STD_LOGIC ;
signal StateMachine_OE			: STD_LOGIC ;

signal MUX_OUT						: STD_LOGIC_VECTOR(15 DOWNTO 0) ;
signal Mux_Sel						: STD_LOGIC ;
signal Bus_Sel						: STD_LOGIC ;

signal SM_ADDRESS					: STD_LOGIC_VECTOR(22 DOWNTO 0) ;

signal MAN_DATA					: STD_LOGIC_VECTOR(15 DOWNTO 0) ;

signal RESET_COMMAND				: STD_LOGIC ;
signal CONT_LED0					: STD_LOGIC ;

component DECODE_MAN 
	port	(
			-- Miscellaneous Signals

			DIN_PRI					:  in	 STD_LOGIC ;
	   	DIN_SEC					:  in  STD_LOGIC ;
	   	TEST_OUT					:  out STD_LOGIC ;
			CLK16						:  in  STD_LOGIC ;
			MAN_DATA					:	out STD_LOGIC_VECTOR(15 downto 0) ;
			reset_button			:	in  STD_LOGIC ;
			LED1_SEL					:	out STD_LOGIC ;
			LED2_SEL					:	out STD_LOGIC ;
			LED3_SEL					:	out STD_LOGIC ;
			RESET_COMMAND			:	in	 STD_LOGIC ;
			IO6						:  out STD_LOGIC ;
			IO7						:  out STD_LOGIC ;
			IO8						:  out STD_LOGIC ;
			IO9						:  out STD_LOGIC ;
			IO42						:  out STD_LOGIC ;
			IO44						:  out STD_LOGIC ;

			-- StateMachine Specific Signals

			Mux_Sel						: out STD_LOGIC ;
			statemachine_sram_enn	: inout STD_LOGIC ;
			statemachine_we			: inout STD_LOGIC ;
			StateMachine_OE			: inout STD_LOGIC ;
			SM_ADDRESS					: inout STD_LOGIC_VECTOR(22 DOWNTO 0) ;
			SM_WE							: out STD_LOGIC
	     ) ;
	     
end component ;

begin

ASSERT_RESET_COMMAND: process(SP_A, SP_D, SP_WEn, SP_CS1n)
begin
	if(SP_CS1n = '0') then
		if(SP_WEn'event and SP_WEn='1') then
			-- If data is decimal 999 at the reset address then start capture
		  	if ((SP_A & '0') = RESET_ADDR) then
		  		RESET_COMMAND <= not(SP_D(0)) ; -- reset SM
		  	end if ;
		end if ;
	 end if ;
	 
end process ASSERT_RESET_COMMAND ;

LED0_SEL <= RESET_COMMAND ; -- Set led to show data capture in effect

--
--                                                           SRAM_Write_En
--                                                                  |
--                                            ---------------------|>---
--                                           |                          | 
--                 SRAM_Read_En              |                          ---[]  D
--                       |                   |    SRAM_ReADDATA         |
--                  ----<|-------------------|---------------------<|----
--                 |                         |
--   DATA []--------                         |
--                 |       SRAM_Write_Data   |
--                  ----|>-------------------
--
-- 
--
--


--Create 2:1 Multiplexer
--
--                      |\
--   SRAM_Write_Data   -| |
--                      | |- MUX_OUT
--         MAN_DATA    -| |
--                      |/
--                       |
--                      Mux_Sel

MUX_OUT(15 DOWNTO 0) <= SRAM_Write_Data(15 DOWNTO 0) when Bus_Sel = '0' else
								MAN_DATA ;


-- Enable Signal		
SRAM_Write_En <= SM_WE or (not SM_WE and ( not SP_WEn and (not SP_CS0n or not SP_CS1n))) ; 


-- Bidirectional Bus, D (Goes TO/FROM the SRAM/FLASH Data bus):

D(15 DOWNTO 0) <=  MUX_OUT(15 DOWNTO 0) when (SRAM_Write_En = '1') else (others => 'Z') ;

SRAM_READDATA(15 DOWNTO 0) <= D(15 DOWNTO 0) ;


SRAM_Read_En <= not SP_OEn and (not SP_CS0n or not SP_CS1n) ;  --  Enable Signal

-- Bidirectional Bus, DATA (Goes TO/FROM Handspring Unit):
SP_D(15 DOWNTO 0) <= SRAM_READDATA(15 DOWNTO 0) when (SRAM_Read_En = '1') else (others => 'Z') ;

SRAM_Write_Data(15 DOWNTO 0) <= SP_D(15 DOWNTO 0) ;

	
--************************************************************************

--Create 2:1 Multiplexer
--
--                      |\
--	   	  		SP_CS1n -| |
--                      | |- SRAM_CS1n
--StateMachine_SRAM_Enn-| |
--                      |/
--                       |
--                      Mux_Sel

SRAM_CS1n <= SP_CS1n when Bus_Sel = '0' else
	  StateMachine_SRAM_Enn ;


--Create 2:1 Multiplexer
--
--                      |\
--				    SP_WEn -| |
--                      | |- RWn
--     StateMachine_WE -| |
--                      |/
--                       |
--                      Mux_Sel

RWn <= SP_WEn when Bus_Sel = '0' else
			  StateMachine_WE ;


--Create 2:1 Multiplexer
--
--                      |\
--	      		SP_OEn  -| |
--                      | |- OEn
--		StateMachine_OE  -| |
--                      |/
--                       |
--                      Mux_Sel

OEn <= SP_OEn when Bus_Sel = '0' else
	  StateMachine_OE ;



--Create 2:1 Multiplexer
--
--                      |\
--               SP_A  -| |
--                      | |- A
--         Addr_count  -| |
--                      |/
--                       |
--                      Mux_Sel

A(22 DOWNTO 0) <= SP_A(23 DOWNTO 1) when Bus_Sel = '0' else
			  SM_ADDRESS ;

SP_A_0 <= '0' ;  --  SP_A(0) is not used in the Springboard Port

-- Allow Handspring access to flash whenever it wants.     
Bus_Sel <= (Mux_Sel and SP_CS0n) ;

--SRAM Control Signals
SRAM_UPPER_BYTEn	<= '0' ;
SRAM_LOW_BYTEn		<= '0' ;

--Flash Control Signals
--FLASH_CS0n 	<= '1' ;
FLASH_CS0n 	<= SP_CS0n ;
FLASH_WR_PROTECT	<= '1' ;
RESET_MEMn <= '1' ;

--Miscellaneous
--IO13		<= SP_CS1n ;    -- Brings CS1 to an outside pin so we can probe it
--IO14 		<= SRAM_CS1n ;

-- *************************** State Machine Instantiation *******************
DVM : DECODE_MAN
  port map(
		--Data Signals
 	   DIN_PRI			=>	  DIN_PRI,
 	   DIN_SEC			=>	  DIN_SEC,
		TEST_OUT			=>	  TEST_OUT,
		CLK16				=>   CLK16,
		MAN_DATA			=>   MAN_DATA,
		reset_button	=>   reset_button,
		LED1_SEL			=>	  LED1_SEL,
		LED2_SEL			=>	  LED2_SEL,
		LED3_SEL			=>	  LED3_SEL,
		RESET_COMMAND	=>	  RESET_COMMAND,
		IO6				=>	  IO6,
		IO7				=>	  IO7,
		IO8				=>	  IO8,
		IO9				=>	  IO9,
		IO42				=>	  IO42,
		IO44				=>	  IO44,

		-- State Machine Signals
		Mux_Sel						=>  Mux_Sel,
		statemachine_sram_enn 	=>  statemachine_sram_enn,
		statemachine_we		  	=>  statemachine_we,
		StateMachine_OE		 	=>  StateMachine_OE,
		SM_ADDRESS					=>  SM_ADDRESS,
 		SM_WE							=>  SM_WE

		);

END BEHAVE;