top_level.prt

xilinx reference design for 1553B BUS analyer using

Setting sync clock limit to 999.
Gct[0] comes from: block 1's CT7 (pt 294)
Gct[1] comes from: block 2's CT7 (pt 404)
Gct[3] comes from: block 4's CT7 (pt 47)

Pre-assignments saved.

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|  P a r t i t i o n i n g . . .  , Seed = 0, Approach = 0, state = 1, GrpAlg=0  |
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Check Pin-locking? Yes (Approach = -1); Timing-driven partition? No

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|  P a r t i t i o n    S u c c e e d  |
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0 Group(s)

ClkInput[1]: clk16(A10, sclk) 
GOE: 404
GRST: 47
GACLK: 294
----------------- B l o c k 0 ------------------
PLApt(48/48), Fanin(29/39), Clk(1/2), Bct(0/8), Pin(8/10), Mcell(15/16), FbNand(0/0)
PLApts[48/48] 24 297 176 187 386 177 298 188 387 178 299 189 179 300 388 345 180 301 158 346 181 302 159 468 
              160 347 303 469 161 348 183 304 382 349 184 305 383 174 350 185 317 306 295 296 175 186 351 197
Fanins[29] N2267.n N_PZ_4074.n N_PZ_4100.n N_PZ_4224.n dvm_I_sm_address_0.n dvm_I_sm_address_1.n 
           dvm_I_sm_address_2.n dvm_I_sm_address_3.n dvm_I_sm_address_4.n dvm_I_sm_address_5.n 
           dvm_I_sm_address_6.n dvm_I_sm_address_7.n dvm_I_sm_address_8.n dvm_main_curr_state_FFD1.n 
           dvm_main_curr_state_FFD2.n dvm_main_curr_state_FFD3.n dvm_main_curr_state_FFD4.n 
           dvm_sram_message_ptr_0.n dvm_sram_message_ptr_1.n dvm_sram_message_ptr_2.n 
           dvm_sram_message_ptr_3.n dvm_sram_message_ptr_4.n dvm_sram_message_ptr_5.n 
           dvm_sram_message_ptr_6.n dvm_sram_message_ptr_7.n dvm_sram_message_ptr_8.n 
           dvm_sram_message_ptr_9.n d[15].p reset_button.p
clk[1/1] clk16 
BCTpts[0] 
Signal[22] [sp_d[15](283),sp_d[15](F15)] [sp_a[10](F17)] [sp_a[14](E18)] [sp_a[19](E19)] [sp_a[20](F19)]  
           [sp_cs1n(G16)] [sp_oen(G17)] [sp_wen(F18)] [dvm_I_sm_address_0(291)] [dvm_I_sm_address_8(290)]  
           [N_PZ_4200(289)] [dvm_I_sm_address_7(288)] [dvm_I_sm_address_6(287)] [dvm_I_sm_address_5(286)]  
           [dvm_I_sm_address_4(296)] [dvm_I_sm_address_3(295)] [dvm_I_sm_address_2(294)]  
           [dvm_sram_message_ptr_5(293)] [dvm_I_sm_address_1(292)] [dvm_sram_message_ptr_4(285)]  
           [dvm_sram_message_ptr_8(284)] [dvm_sram_message_ptr_9(282)] 
FbNand[ 0] 
----------------- B l o c k 1 ------------------
PLApt(38/48), Fanin(30/39), Clk(1/2), Bct(1/8), Pin(10/10), Mcell(16/16), FbNand(0/0)
PLApts[38/38] 294 165 407 308 418 166 408 309 419 167 409 310 420 200 410 311 421 190 201 312 422 202 423 203 
              424 204 193 425 194 162 195 163 405 196 164 406 307 318
Fanins[30] N2267.n N_PZ_4074.n N_PZ_4200.n dvm_I_sm_address_10.n dvm_I_sm_address_11.n dvm_I_sm_address_12.n 
           dvm_I_sm_address_13.n dvm_I_sm_address_14.n dvm_I_sm_address_15.n dvm_I_sm_address_9.n 
           dvm_main_curr_state_FFD1.n dvm_main_curr_state_FFD2.n dvm_main_curr_state_FFD4.n 
           dvm_sram_message_ptr_10.n dvm_sram_message_ptr_11.n dvm_sram_message_ptr_12.n 
           dvm_sram_message_ptr_13.n dvm_sram_message_ptr_14.n dvm_sram_message_ptr_15.n 
           dvm_sram_message_ptr_9.n d[11].p d[12].p d[13].p d[14].p d[3].p d[4].p d[5].p d[6].p d[7].p 
           reset_button.p
clk[1/1] clk16 
BCTpts[1] ct7:294 
Signal[17] [sp_d[11](308),sp_d[11](C16)] [sp_d[12](309),sp_d[12](A16)] [sp_d[13](299),sp_d[13](B17)]  
           [sp_d[14](298),sp_d[14](B18)] [sp_d[3](311),sp_d[3](D15)] [sp_d[4](310),sp_d[4](E15)]  
           [sp_d[5](312),sp_d[5](A15)] [sp_d[6](301),sp_d[6](A17)] [sp_d[7](300),sp_d[7](A18)]  
           [sp_cs0n(B19)] [dvm_I_sm_address_9(307)] [dvm_I_sm_address_10(306)] [dvm_I_sm_address_11(305)]  
           [dvm_I_sm_address_12(304)] [dvm_I_sm_address_13(303)] [dvm_I_sm_address_14(302)]  
           [dvm_I_sm_address_15(297)] 
FbNand[ 0] 
----------------- B l o c k 2 ------------------
PLApt(48/48), Fanin(36/39), Clk(1/2), Bct(1/8), Pin(8/10), Mcell(16/16), FbNand(0/0)
PLApts[48/48] 404 363 22 429 133 12 430 134 431 135 366 377 432 168 367 378 389 169 411 379 390 170 412 313 
              380 391 171 413 314 480 392 414 315 481 393 415 316 426 361 64 482 394 416 427 362 483 417 428
Fanins[36] N2267.n N_PZ_4074.n N_PZ_4112.n N_PZ_4200.n N_PZ_4280.n dvm_I_sm_address_10.n 
           dvm_I_sm_address_11.n dvm_I_sm_address_12.n dvm_I_sm_address_13.n dvm_I_sm_address_14.n 
           dvm_I_sm_address_15.n dvm_I_sm_address_16.n dvm_I_sm_address_17.n dvm_I_sm_address_18.n 
           dvm_I_sm_address_19.n dvm_I_sm_address_20.n dvm_I_sm_address_21.n dvm_I_sm_address_22.n 
           dvm_I_sm_address_9.n dvm_clock_count_0.n dvm_main_curr_state_FFD1.n dvm_main_curr_state_FFD2.n 
           dvm_main_curr_state_FFD3.n dvm_main_curr_state_FFD4.n dvm_pwclock_count_0.n dvm_pwclock_count_1.n 
           dvm_sram_message_ptr_0.n dvm_sram_message_ptr_1.n dvm_sram_message_ptr_16.n 
           dvm_sram_message_ptr_17.n dvm_sram_message_ptr_18.n dvm_sram_message_ptr_19.n 
           dvm_sram_message_ptr_20.n dvm_sram_message_ptr_21.n dvm_sram_message_ptr_22.n reset_button.p
clk[1/1] clk16 
BCTpts[1] ct7:404 
Signal[24] [sp_a[11](H17)] [sp_a[15](K18)] [sp_a[16](H19)] [sp_a[17](L16)] [sp_a[21](H18)] [sp_a[22](J18)]  
           [sp_a[8](K17)] [sp_a[9](J17)] [dvm_I_sm_address_16(323)] [dvm_I_sm_address_17(322)]  
           [dvm_I_sm_address_18(321)] [dvm_I_sm_address_19(320)] [dvm_I_sm_address_20(319)]  
           [dvm_I_sm_address_21(318)] [dvm_I_sm_address_22(328)] [dvm_sram_message_ptr_22(327)]  
           [dvm_sram_message_ptr_21(326)] [dvm_sram_message_ptr_20(325)] [dvm_sram_message_ptr_19(324)]  
           [dvm_sram_message_ptr_0(317)] [dvm_sram_message_ptr_1(316)] [dvm_clock_count_0(315)]  
           [dvm_pwclock_count_0(314)] [dvm_pwclock_count_1(313)] 
FbNand[ 0] 
----------------- B l o c k 3 ------------------
PLApt(31/48), Fanin(38/39), Clk(1/2), Bct(2/8), Pin(9/10), Mcell(16/16), FbNand(0/0)
PLApts[31/31] 5403 95 97 99 286 100 276 287 232 101 233 234 278 26 4 246 279 434 5 247 435 6 248 292 249 293 
              250 240 208 241 285
Fanins[38] N851.n N_PZ_4072.n N_PZ_4077.n N_PZ_4115.n dvm_I_man_data_0.n dvm_I_man_data_1.n 
           dvm_I_man_data_10.n dvm_I_man_data_2.n dvm_I_man_data_3.n dvm_I_man_data_8.n dvm_I_man_data_9.n 
           dvm_I_statemachine_oe.n dvm_clock_count_0.n dvm_clock_count_1.n dvm_clock_count_2.n 
           dvm_clock_count_3.n dvm_clock_count_4.n dvm_clock_count_5.n dvm_data1.n dvm_data2.n dvm_data3.n 
           dvm_main_curr_state_FFD1.n dvm_main_curr_state_FFD2.n dvm_main_curr_state_FFD3.n 
           dvm_main_curr_state_FFD4.n dvm_man_word_0.n dvm_mdi1.n sp_cs0n.p sp_cs1n.p sp_d[0].p sp_d[10].p 
           sp_d[1].p sp_d[2].p sp_d[3].p sp_d[8].p sp_d[9].p sp_oen.p sp_wen.p
clk[1/1] clk16 
BCTpts[2] ct0:5403 ct4:95 
Signal[16] [d[0](331),d[0](A14)] [d[10](343),d[10](B12)] [d[1](333),d[1](B13)] [d[2](344),d[2](D12)]  
           [d[3](341),d[3](A12)] [d[8](332),d[8](C13)] [d[9](340),d[9](A13)] [oen(330),oen(D14)]  
           [flash_cs0n(329),flash_cs0n(E14)] [N_PZ_4077(342)] [N_PZ_4112(339)] [N_PZ_4115(338)]  
           [dvm_mdi2(337)] [dvm_data1(336)] [dvm_data2(335)] [dvm_man_word_0(334)] 
FbNand[ 0] 
----------------- B l o c k 4 ------------------
PLApt(18/48), Fanin(17/39), Clk(1/2), Bct(2/8), Pin(7/10), Mcell(16/16), FbNand(0/0)
PLApts[18/18] 48 47 55 56 57 58 59 60 49 61 50 62 51 63 52 30 53 54
Fanins[17] led0_sel.n dvm_time_counter_0.n dvm_time_counter_1.n dvm_time_counter_10.n dvm_time_counter_11.n 
           dvm_time_counter_12.n dvm_time_counter_13.n dvm_time_counter_14.n dvm_time_counter_2.n 
           dvm_time_counter_3.n dvm_time_counter_4.n dvm_time_counter_5.n dvm_time_counter_6.n 
           dvm_time_counter_7.n dvm_time_counter_8.n dvm_time_counter_9.n reset_button.p
clk[1/1] clk16 
BCTpts[2] ct4:48 ct7:47 
Signal[23] [sp_a[12](M18)] [sp_a[13](L17)] [sp_a[18](M17)] [sp_a[23](L18)] [sp_a[4](N16)] [sp_a[5](M16)]  
           [sp_a[7](N18)] [dvm_time_counter_1(347)] [dvm_time_counter_0(355)] [dvm_time_counter_2(354)]  
           [dvm_time_counter_3(353)] [dvm_time_counter_4(352)] [dvm_time_counter_5(351)]  
           [dvm_time_counter_6(350)] [dvm_time_counter_7(360)] [dvm_time_counter_8(359)]  
           [dvm_time_counter_9(358)] [dvm_time_counter_10(357)] [dvm_time_counter_11(356)]  
           [dvm_time_counter_12(349)] [dvm_time_counter_13(348)] [dvm_time_counter_14(346)]  
           [dvm_time_counter_15(345)] 
FbNand[ 0] 
----------------- B l o c k 5 ------------------
PLApt(32/48), Fanin(26/39), Clk(1/2), Bct(0/8), Pin(0/10), Mcell(16/16), FbNand(0/0)
PLApts[32/32] 385 473 374 364 474 375 24 475 376 476 136 180 466 477 137 467 368 478 182 369 479 381 172 370 
              173 470 371 471 372 384 472 373
Fanins[26] N_PZ_4074.n N_PZ_4224.n dvm_main_curr_state_FFD1.n dvm_main_curr_state_FFD2.n 
           dvm_main_curr_state_FFD3.n dvm_main_curr_state_FFD4.n dvm_pwclock_count_0.n dvm_pwclock_count_1.n 
           dvm_pwclock_count_2.n dvm_sram_message_ptr_10.n dvm_sram_message_ptr_11.n 
           dvm_sram_message_ptr_12.n dvm_sram_message_ptr_13.n dvm_sram_message_ptr_14.n 
           dvm_sram_message_ptr_15.n dvm_sram_message_ptr_16.n dvm_sram_message_ptr_17.n 
           dvm_sram_message_ptr_18.n dvm_sram_message_ptr_2.n dvm_sram_message_ptr_3.n 
           dvm_sram_message_ptr_4.n dvm_sram_message_ptr_5.n dvm_sram_message_ptr_6.n 
           dvm_sram_message_ptr_7.n dvm_sram_message_ptr_8.n dvm_sram_message_ptr_9.n
clk[1/1] clk16 
BCTpts[0] 
Signal[16] [dvm_sram_message_ptr_18(371)] [dvm_sram_message_ptr_17(370)] [dvm_sram_message_ptr_16(369)]  
           [dvm_sram_message_ptr_15(368)] [dvm_sram_message_ptr_14(367)] [dvm_sram_message_ptr_13(366)]  
           [N_PZ_4280(376)] [dvm_sram_message_ptr_12(375)] [dvm_sram_message_ptr_11(374)]  
           [dvm_sram_message_ptr_10(373)] [dvm_sram_message_ptr_7(372)] [dvm_sram_message_ptr_6(365)]  
           [dvm_sram_message_ptr_3(364)] [dvm_sram_message_ptr_2(363)] [N_PZ_4224(362)]  
           [dvm_pwclock_count_2(361)] 
FbNand[ 0] 
----------------- B l o c k 6 ------------------
PLApt(48/48), Fanin(34/39), Clk(1/2), Bct(2/8), Pin(6/10), Mcell(15/16), FbNand(0/0)
PLApts[48/48] 5048 48 143 11 154 330 341 319 132 352 144 331 342 320 155 354 145 332 343 156 13 344 333 157 
              334 356 335 357 402 336 28 17 359 150 337 18 360 151 338 206 152 339 9 153 329 340 21 10
Fanins[34] led0_sel.n N1106.n N2273.n N2278.n N2364.n N2406.n N_PZ_4074.n N_PZ_4100.n N_PZ_4264.n 
           dvm_command_status_0.n dvm_command_status_1.n dvm_data3.n dvm_main_curr_state_FFD1.n 
           dvm_main_curr_state_FFD2.n dvm_main_curr_state_FFD3.n dvm_main_curr_state_FFD4.n dvm_mdi1.n 
           dvm_mdi2.n dvm_mdi3.n dvm_pwclock_count_0.n dvm_pwclock_count_1.n dvm_pwclock_count_2.n