📄 time_sim.vhd
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dvm_sram_message_ptr_15_C, dvm_sram_message_ptr_15_DIN,
dvm_sram_message_ptr_15_Q, dvm_sram_message_ptr_15_Q_tF,
dvm_sram_message_ptr_15_T, dvm_sram_message_ptr_16_AP,
dvm_sram_message_ptr_16_AR, dvm_sram_message_ptr_16_C,
dvm_sram_message_ptr_16_DIN, dvm_sram_message_ptr_16_Q,
dvm_sram_message_ptr_16_Q_tF, dvm_sram_message_ptr_16_T,
dvm_sram_message_ptr_17_AP, dvm_sram_message_ptr_17_AR,
dvm_sram_message_ptr_17_C, dvm_sram_message_ptr_17_DIN,
dvm_sram_message_ptr_17_Q, dvm_sram_message_ptr_17_Q_tF,
dvm_sram_message_ptr_17_T, dvm_sram_message_ptr_18_AP,
dvm_sram_message_ptr_18_AR, dvm_sram_message_ptr_18_C,
dvm_sram_message_ptr_18_DIN, dvm_sram_message_ptr_18_Q,
dvm_sram_message_ptr_18_Q_tF, dvm_sram_message_ptr_18_T,
dvm_sram_message_ptr_19_AP, dvm_sram_message_ptr_19_AR,
dvm_sram_message_ptr_19_C, dvm_sram_message_ptr_19_DIN,
dvm_sram_message_ptr_19_Q, dvm_sram_message_ptr_19_Q_tF,
dvm_sram_message_ptr_19_T, dvm_sram_message_ptr_1_AP,
dvm_sram_message_ptr_1_AR, dvm_sram_message_ptr_1_C,
dvm_sram_message_ptr_1_DIN, dvm_sram_message_ptr_1_Q,
dvm_sram_message_ptr_1_Q_tF, dvm_sram_message_ptr_1_T,
dvm_sram_message_ptr_20_AP, dvm_sram_message_ptr_20_AR,
dvm_sram_message_ptr_20_C, dvm_sram_message_ptr_20_DIN,
dvm_sram_message_ptr_20_Q, dvm_sram_message_ptr_20_Q_tF,
dvm_sram_message_ptr_20_T, dvm_sram_message_ptr_21_AP,
dvm_sram_message_ptr_21_AR, dvm_sram_message_ptr_21_C,
dvm_sram_message_ptr_21_DIN, dvm_sram_message_ptr_21_Q,
dvm_sram_message_ptr_21_Q_tF, dvm_sram_message_ptr_21_T,
dvm_sram_message_ptr_22_AP, dvm_sram_message_ptr_22_AR,
dvm_sram_message_ptr_22_C, dvm_sram_message_ptr_22_DIN,
dvm_sram_message_ptr_22_Q, dvm_sram_message_ptr_22_Q_tF,
dvm_sram_message_ptr_22_T, dvm_sram_message_ptr_2_AP,
dvm_sram_message_ptr_2_AR, dvm_sram_message_ptr_2_C,
dvm_sram_message_ptr_2_DIN, dvm_sram_message_ptr_2_Q,
dvm_sram_message_ptr_2_Q_tF, dvm_sram_message_ptr_2_T,
dvm_sram_message_ptr_3_AP, dvm_sram_message_ptr_3_AR,
dvm_sram_message_ptr_3_C, dvm_sram_message_ptr_3_DIN,
dvm_sram_message_ptr_3_Q, dvm_sram_message_ptr_3_Q_tF,
dvm_sram_message_ptr_3_T, dvm_sram_message_ptr_4_AP,
dvm_sram_message_ptr_4_AR, dvm_sram_message_ptr_4_C,
dvm_sram_message_ptr_4_DIN, dvm_sram_message_ptr_4_Q,
dvm_sram_message_ptr_4_Q_tF, dvm_sram_message_ptr_4_T,
dvm_sram_message_ptr_5_AP, dvm_sram_message_ptr_5_AR,
dvm_sram_message_ptr_5_C, dvm_sram_message_ptr_5_DIN,
dvm_sram_message_ptr_5_Q, dvm_sram_message_ptr_5_Q_tF,
dvm_sram_message_ptr_5_T, dvm_sram_message_ptr_6_AP,
dvm_sram_message_ptr_6_AR, dvm_sram_message_ptr_6_C,
dvm_sram_message_ptr_6_DIN, dvm_sram_message_ptr_6_Q,
dvm_sram_message_ptr_6_Q_tF, dvm_sram_message_ptr_6_T,
dvm_sram_message_ptr_7_AP, dvm_sram_message_ptr_7_AR,
dvm_sram_message_ptr_7_C, dvm_sram_message_ptr_7_DIN,
dvm_sram_message_ptr_7_Q, dvm_sram_message_ptr_7_Q_tF,
dvm_sram_message_ptr_7_T, dvm_sram_message_ptr_8_AP,
dvm_sram_message_ptr_8_AR, dvm_sram_message_ptr_8_C,
dvm_sram_message_ptr_8_DIN, dvm_sram_message_ptr_8_Q,
dvm_sram_message_ptr_8_Q_tF, dvm_sram_message_ptr_8_T,
dvm_sram_message_ptr_9_AP, dvm_sram_message_ptr_9_AR,
dvm_sram_message_ptr_9_C, dvm_sram_message_ptr_9_DIN,
dvm_sram_message_ptr_9_Q, dvm_sram_message_ptr_9_Q_tF,
dvm_sram_message_ptr_9_T, dvm_time_counter_0_AP,
dvm_time_counter_0_AR, dvm_time_counter_0_C,
dvm_time_counter_0_CE, dvm_time_counter_0_D,
dvm_time_counter_0_DIN, dvm_time_counter_0_Q,
dvm_time_counter_0_Q_tF, dvm_time_counter_10_AP,
dvm_time_counter_10_AR, dvm_time_counter_10_C,
dvm_time_counter_10_DIN, dvm_time_counter_10_Q,
dvm_time_counter_10_Q_tF, dvm_time_counter_10_T,
dvm_time_counter_11_AP, dvm_time_counter_11_AR,
dvm_time_counter_11_C, dvm_time_counter_11_DIN,
dvm_time_counter_11_Q, dvm_time_counter_11_Q_tF,
dvm_time_counter_11_T, dvm_time_counter_12_AP,
dvm_time_counter_12_AR, dvm_time_counter_12_C,
dvm_time_counter_12_DIN, dvm_time_counter_12_Q,
dvm_time_counter_12_Q_tF, dvm_time_counter_12_T,
dvm_time_counter_13_AP, dvm_time_counter_13_AR,
dvm_time_counter_13_C, dvm_time_counter_13_DIN,
dvm_time_counter_13_Q, dvm_time_counter_13_Q_tF,
dvm_time_counter_13_T, dvm_time_counter_14_AP,
dvm_time_counter_14_AR, dvm_time_counter_14_C,
dvm_time_counter_14_DIN, dvm_time_counter_14_Q,
dvm_time_counter_14_Q_tF, dvm_time_counter_14_T,
dvm_time_counter_15_AP, dvm_time_counter_15_AR,
dvm_time_counter_15_C, dvm_time_counter_15_DIN,
dvm_time_counter_15_Q, dvm_time_counter_15_Q_tF,
dvm_time_counter_15_T, dvm_time_counter_1_AP,
dvm_time_counter_1_AR, dvm_time_counter_1_C,
dvm_time_counter_1_DIN, dvm_time_counter_1_Q,
dvm_time_counter_1_Q_tF, dvm_time_counter_1_T,
dvm_time_counter_2_AP, dvm_time_counter_2_AR,
dvm_time_counter_2_C, dvm_time_counter_2_DIN,
dvm_time_counter_2_Q, dvm_time_counter_2_Q_tF,
dvm_time_counter_2_T, dvm_time_counter_3_AP,
dvm_time_counter_3_AR, dvm_time_counter_3_C,
dvm_time_counter_3_DIN, dvm_time_counter_3_Q,
dvm_time_counter_3_Q_tF, dvm_time_counter_3_T,
dvm_time_counter_4_AP, dvm_time_counter_4_AR,
dvm_time_counter_4_C, dvm_time_counter_4_DIN,
dvm_time_counter_4_Q, dvm_time_counter_4_Q_tF,
dvm_time_counter_4_T, dvm_time_counter_5_AP,
dvm_time_counter_5_AR, dvm_time_counter_5_C,
dvm_time_counter_5_DIN, dvm_time_counter_5_Q,
dvm_time_counter_5_Q_tF, dvm_time_counter_5_T,
dvm_time_counter_6_AP, dvm_time_counter_6_AR,
dvm_time_counter_6_C, dvm_time_counter_6_DIN,
dvm_time_counter_6_Q, dvm_time_counter_6_Q_tF,
dvm_time_counter_6_T, dvm_time_counter_7_AP,
dvm_time_counter_7_AR, dvm_time_counter_7_C,
dvm_time_counter_7_DIN, dvm_time_counter_7_Q,
dvm_time_counter_7_Q_tF, dvm_time_counter_7_T,
dvm_time_counter_8_AP, dvm_time_counter_8_AR,
dvm_time_counter_8_C, dvm_time_counter_8_DIN,
dvm_time_counter_8_Q, dvm_time_counter_8_Q_tF,
dvm_time_counter_8_T, dvm_time_counter_9_AP,
dvm_time_counter_9_AR, dvm_time_counter_9_C,
dvm_time_counter_9_DIN, dvm_time_counter_9_Q,
dvm_time_counter_9_Q_tF, dvm_time_counter_9_T, dvm_x_n0040_AP,
dvm_x_n0040_AR, dvm_x_n0040_D, dvm_x_n0040_DIN, dvm_x_n0040_LE,
dvm_x_n0040_Q, dvm_x_n0040_Q_tF, flash_cs0n_COM, flash_cs0n_OE,
flash_wr_protect_COM, flash_wr_protect_OE, io42_COM, io42_OE,
io44_COM, io44_OE, io6_COM, io6_OE, io7_COM, io7_OE, io8_COM,
io8_OE, io9_COM, io9_OE, led0_sel_AP, led0_sel_AR, led0_sel_C,
led0_sel_CE, led0_sel_D, led0_sel_DIN, led0_sel_OE, led0_sel_Q,
led0_sel_Q_tF, led1_sel_COM, led1_sel_OE, led2_sel_COM,
led2_sel_OE, led3_sel_COM, led3_sel_OE, oen_COM, oen_OE,
reset_button_tIN, reset_memn_COM, reset_memn_OE, rwn_COM, rwn_OE,
sp_a_0_COM, sp_a_0_OE, sp_a_10_tIN, sp_a_11_tIN, sp_a_12_tIN,
sp_a_13_tIN, sp_a_14_tIN, sp_a_15_tIN, sp_a_16_tIN, sp_a_17_tIN,
sp_a_18_tIN, sp_a_19_tIN, sp_a_1_tIN, sp_a_20_tIN, sp_a_21_tIN,
sp_a_22_tIN, sp_a_23_tIN, sp_a_2_tIN, sp_a_3_tIN, sp_a_4_tIN,
sp_a_5_tIN, sp_a_6_tIN, sp_a_7_tIN, sp_a_8_tIN, sp_a_9_tIN,
sp_cs0n_tIN, sp_cs1n_tIN, sp_d_0_COM, sp_d_0_OE, sp_d_0_tIN,
sp_d_10_COM, sp_d_10_OE, sp_d_10_tIN, sp_d_11_COM, sp_d_11_OE,
sp_d_11_tIN, sp_d_12_COM, sp_d_12_OE, sp_d_12_tIN, sp_d_13_COM,
sp_d_13_OE, sp_d_13_tIN, sp_d_14_COM, sp_d_14_OE, sp_d_14_tIN,
sp_d_15_COM, sp_d_15_OE, sp_d_15_tIN, sp_d_1_COM, sp_d_1_OE,
sp_d_1_tIN, sp_d_2_COM, sp_d_2_OE, sp_d_2_tIN, sp_d_3_COM,
sp_d_3_OE, sp_d_3_tIN, sp_d_4_COM, sp_d_4_OE, sp_d_4_tIN,
sp_d_5_COM, sp_d_5_OE, sp_d_5_tIN, sp_d_6_COM, sp_d_6_OE,
sp_d_6_tIN, sp_d_7_COM, sp_d_7_OE, sp_d_7_tIN, sp_d_8_COM,
sp_d_8_OE, sp_d_8_tIN, sp_d_9_COM, sp_d_9_OE, sp_d_9_tIN,
sp_oen_tIN, sp_wen_tIN, sram_cs1n_COM, sram_cs1n_OE,
sram_low_byten_COM, sram_low_byten_OE, sram_upper_byten_COM,
sram_upper_byten_OE, test_out_COM, test_out_OE: std_logic;
signal VCC : std_logic;
signal GND : std_logic;
component pxa_bufif2
port (O: out std_logic; I, OE, SLEW : in std_logic);
end component;
component pxa_mux
port (O: out std_logic; S, A, B : in std_logic);
end component;
component pxa_dff_apar_p0
port (Q : out std_logic; D, CLK, AP, AR : in std_logic);
end component;
component pxa_tff_apar_p0
port (Q : out std_logic; T, CLK, AP, AR : in std_logic);
end component;
component pxa_dff_ce_apar_p0
port (Q : out std_logic; D, CLK, CE, AP, AR : in std_logic);
end component;
component pxa_lff_apar_p0
port (Q : out std_logic; D, LH, AP, AR : in std_logic);
end component;
begin
-- Equations:
VCC <= '1';
GND <= '0';
--------( N1106 )----------------------------------------------------------
N1106_COM <= not ((not dvm_main_curr_state_FFD2_Q_tF
and not dvm_main_curr_state_FFD3_Q_tF
and not dvm_main_curr_state_FFD1_Q_tF
and not dvm_main_curr_state_FFD4_Q_tF)) after tLOGI1;
--------( N2267 )----------------------------------------------------------
N2267_COM <= ((dvm_main_curr_state_FFD4_Q_tF
and dvm_main_curr_state_FFD3_Q_tF
and dvm_main_curr_state_FFD1_Q_tF
and not dvm_main_curr_state_FFD2_Q_tF)
or (dvm_main_curr_state_FFD4_Q_tF
and not dvm_main_curr_state_FFD3_Q_tF
and not dvm_main_curr_state_FFD1_Q_tF
and not dvm_main_curr_state_FFD2_Q_tF)) after tLOGI2;
--------( N2273 )----------------------------------------------------------
N2273_COM <= ((dvm_clock_count_3_Q_tF and dvm_main_curr_state_FFD3_Q_tF
and dvm_clock_count_5_Q_tF and not dvm_clock_count_2_Q_tF
and not dvm_clock_count_4_Q_tF and dvm_data1_Q_tF
and dvm_main_curr_state_FFD2_Q_tF
and not dvm_clock_count_1_Q_tF
and not dvm_clock_count_0_Q_tF
and dvm_main_curr_state_FFD1_Q_tF
and dvm_main_curr_state_FFD4_Q_tF)
or (dvm_clock_count_3_Q_tF
and dvm_main_curr_state_FFD3_Q_tF
and dvm_clock_count_5_Q_tF and not dvm_clock_count_2_Q_tF
and not dvm_clock_count_4_Q_tF
and dvm_main_curr_state_FFD2_Q_tF
and not dvm_clock_count_1_Q_tF and dvm_data2_Q_tF
and not dvm_clock_count_0_Q_tF
and dvm_main_curr_state_FFD1_Q_tF
and dvm_main_curr_state_FFD4_Q_tF)) after tLOGI2;
--------( N2278 )----------------------------------------------------------
N2278_COM <= not ((dvm_main_curr_state_FFD3_Q_tF and dvm_mdi1_Q_tF
and dvm_main_curr_state_FFD1_Q_tF
and not dvm_main_curr_state_FFD4_Q_tF and not dvm_mdi3_Q_tF
and dvm_main_curr_state_FFD2_Q_tF)) after tLOGI1;
--------( N2364 )----------------------------------------------------------
N2364_COM <= ((dvm_main_curr_state_FFD1_Q_tF
and dvm_main_curr_state_FFD4_Q_tF
and not dvm_main_curr_state_FFD3_Q_tF)
or (dvm_main_curr_state_FFD1_Q_tF
and not dvm_main_curr_state_FFD2_Q_tF
and not dvm_main_curr_state_FFD3_Q_tF)
or (not dvm_main_curr_state_FFD1_Q_tF
and dvm_main_curr_state_FFD4_Q_tF
and dvm_main_curr_state_FFD3_Q_tF)
or (not dvm_main_curr_state_FFD1_Q_tF
and not dvm_main_curr_state_FFD4_Q_tF
and not dvm_main_curr_state_FFD2_Q_tF)
or (dvm_rclock_count_7_Q_tF and dvm_rclock_count_2_Q_tF
and not dvm_mdi1_Q_tF and dvm_main_curr_state_FFD1_Q_tF
and dvm_rclock_count_4_Q_tF and dvm_rclock_count_3_Q_tF
and not dvm_main_curr_state_FFD4_Q_tF
and dvm_rclock_count_1_Q_tF
and dvm_main_curr_state_FFD2_Q_tF
and not dvm_rclock_count_5_Q_tF and dvm_rclock_count_0_Q_tF
and dvm_rclock_count_6_Q_tF
and not dvm_main_curr_state_FFD3_Q_tF)
or (dvm_rclock_count_7_Q_tF and dvm_rclock_count_2_Q_tF
and dvm_main_curr_state_FFD1_Q_tF
and dvm_rclock_count_4_Q_tF and dvm_rclock_count_3_Q_tF
and not dvm_main_curr_state_FFD4_Q_tF and dvm_mdi3_Q_tF
and dvm_rclock_count_1_Q_tF
and dvm_main_curr_state_FFD2_Q_tF
and not dvm_rclock_count_5_Q_tF and dvm_rclock_count_0_Q_tF
and dvm_rclock_count_6_Q_tF
and not dvm_main_curr_state_FFD3_Q_tF)
or (not N2278_COM_tF)
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