time_sim.vhd

xilinx reference design for 1553B BUS analyer using

---------------------------------------------------------------------------
-- XPLAOPT Version 3.45
-- VHDL Timing Model
-- Converted from JEDEC file
-- Created by Xilinx, Inc.
-- Design Name = top_level.blx
-- Device Name = XCR3256XL-7CS280
-- Aug 13 15:07:06 2001
---------------------------------------------------------------------------
package pxa_pkg is
    constant tLOGI1 : time := 2000 ps;
    constant tLOGI2 : time := 2500 ps;
    constant tLOGI3 : time := 6000 ps;
    constant tFIN  : time := 2700 ps;
    constant tIN   : time := 2500 ps;
    constant tF    : time := 2800 ps;
    constant tUDA  : time := 4000 ps;
    constant tGCK  : time := 1000 ps;
    constant tLDI  : time := 1300 ps;
    constant toe_slew : time := 8500 ps;
    constant tbuf_slew : time := 6500 ps;
    constant tap2q : time := 2000 ps;
    constant tar2q : time := 2000 ps;
    constant trd   : time := 1000 ps;
    constant tbuf  : time := 2500 ps;
    constant toe   : time := 4500 ps;
end pxa_pkg;
---------------------------------------------------------------------------
-- Components Defined Here
---------------------------------------------------------------------------
-- Output Buffer
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity pxa_bufif2 is
	port (O: out std_logic; I, OE, SLEW : in std_logic);
end pxa_bufif2;
architecture behavioral of pxa_bufif2 is
signal OE_local, I_local : std_logic := '0';
begin
  OE_local <= OE after toe_slew when SLEW = '1' else OE after toe;
  I_local <= I after tbuf_slew when SLEW = '1' else I after tbuf;
  O <= I_local when OE_local = '1' else 'Z';
end behavioral;

-- Multiplexer
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity pxa_mux is
	port (O: out std_logic; S, A, B : in std_logic);
end pxa_mux;
architecture behavioral of pxa_mux is
begin
	O <= A when S = '1' else B;
end behavioral;

-- D Flip Flop with Asynchronous Preset/Reset; Power up to 0.
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity pxa_dff_apar_p0 is
	port (Q : out std_logic; D, CLK, AP, AR : in std_logic);
end pxa_dff_apar_p0;
architecture behavioral of pxa_dff_apar_p0 is
signal Q_local: std_logic := '0';
begin
  process(CLK, AP, AR)
  begin
    if AR = '1' then
	   Q_local <= '0' after tar2q;
    elsif AP = '1' then
	   Q_local <= '1' after tap2q;
    elsif rising_edge(CLK) then
	   Q_local <= D after trd;
    end if;
  end process;
  Q <= Q_local;
end behavioral;

-- T Flip Flop with Asynchronous Preset/Reset; Power up to 0.
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity pxa_tff_apar_p0 is
	port (Q : out std_logic; T, CLK, AP, AR : in std_logic);
end pxa_tff_apar_p0;
architecture behavioral of pxa_tff_apar_p0 is
signal Q_local: std_logic := '0';
begin
  process(CLK, AP, AR)
  begin
    if AR = '1' then
      Q_local <= '0' after tar2q;
    elsif AP = '1' then
      Q_local <= '1' after tap2q;
    elsif rising_edge(CLK) then
      if T = '1' then
        Q_local <= not Q_local after trd ;
      end if;
    end if;
  end process;
  Q <= Q_local;
end behavioral;

-- D Flip Flop with Clock Enable and Asyn Preset/Reset; Power up to 0.
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity pxa_dff_ce_apar_p0 is
	port (Q : out std_logic; D, CLK, CE, AP, AR : in std_logic);
end pxa_dff_ce_apar_p0;
architecture behavioral of pxa_dff_ce_apar_p0 is
signal Q_local: std_logic := '0';
begin
  process(CLK, CE, AP, AR)
  begin
    if AR = '1' then
	   Q_local <= '0' after tar2q;
    elsif AP = '1' then
	   Q_local <= '1' after tap2q;
    elsif rising_edge(CLK) then
      if CE = '1' then
        Q_local <= D after trd;
      end if;
    end if;
  end process;
  Q <= Q_local;
end behavioral;

-- D Latch with Active High Latch Enable/Set/Reset; Power up to 0.
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity pxa_lff_apar_p0 is
	port (Q : out std_logic; D, LH, AP, AR : in std_logic);
end pxa_lff_apar_p0;
architecture behavioral of pxa_lff_apar_p0 is
signal Q_local: std_logic := '0';
begin
  process(D, LH, AP, AR)
  begin
    if AR = '1' then
      Q_local <= '0' after tar2q;
    elsif LH = '1' then
      Q_local <= D after tLDI;
    elsif AP = '1' then
      Q_local <= '1' after tap2q;
    end if;
  end process;
  Q <= Q_local;
end behavioral;

---------------------------------------------------------------------------
-- Main VHDL Model 
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.pxa_pkg.all;
entity top_level is
    port(clk16, din_pri, reset_button, sp_cs0n, sp_cs1n, sp_oen, sp_wen
         : in std_logic;
         sp_a: in std_logic_vector(23 downto 1);
         flash_cs0n, flash_wr_protect, io42, io44, io6, io7, io8, io9,
         led0_sel, led1_sel, led2_sel, led3_sel, oen, reset_memn, rwn,
         sp_a_0, sram_cs1n, sram_low_byten, sram_upper_byten, test_out
         : out std_logic;
         a: out std_logic_vector(22 downto 0);
         d: inout std_logic_vector(15 downto 0);
         sp_d: inout std_logic_vector(15 downto 0)
         );
end top_level;

architecture structure of top_level is

-------- Signal Declaration -----------------------------------------------
signal   N1106_COM, N1106_COM_tF, N2267_COM, N2267_COM_tF, N2273_COM,
         N2273_COM_tF, N2278_COM, N2278_COM_tF, N2364_COM, N2364_COM_tF,
         N2406_COM, N2406_COM_tF, N805_COM, N805_COM_tF, N851_COM,
         N851_COM_tF, N_PZ_4072_COM, N_PZ_4072_COM_tF, N_PZ_4074_COM,
         N_PZ_4074_COM_tF, N_PZ_4077_COM, N_PZ_4077_COM_tF, N_PZ_4100_COM,
         N_PZ_4100_COM_tF, N_PZ_4112_COM, N_PZ_4112_COM_tF, N_PZ_4115_COM,
         N_PZ_4115_COM_tF, N_PZ_4199_COM, N_PZ_4199_COM_tF, N_PZ_4200_COM,
         N_PZ_4200_COM_tF, N_PZ_4224_COM, N_PZ_4224_COM_tF, N_PZ_4264_COM,
         N_PZ_4264_COM_tF, N_PZ_4280_COM, N_PZ_4280_COM_tF, a_0_COM,
         a_0_OE, a_10_COM, a_10_OE, a_11_COM, a_11_OE, a_12_COM, a_12_OE,
         a_13_COM, a_13_OE, a_14_COM, a_14_OE, a_15_COM, a_15_OE, a_16_COM,
         a_16_OE, a_17_COM, a_17_OE, a_18_COM, a_18_OE, a_19_COM, a_19_OE,
         a_1_COM, a_1_OE, a_20_COM, a_20_OE, a_21_COM, a_21_OE, a_22_COM,
         a_22_OE, a_2_COM, a_2_OE, a_3_COM, a_3_OE, a_4_COM, a_4_OE,
         a_5_COM, a_5_OE, a_6_COM, a_6_OE, a_7_COM, a_7_OE, a_8_COM,
         a_8_OE, a_9_COM, a_9_OE, d_0_COM, d_0_OE, d_0_tIN, d_10_COM,
         d_10_OE, d_10_tIN, d_11_COM, d_11_OE, d_11_tIN, d_12_COM, d_12_OE,
         d_12_tIN, d_13_COM, d_13_OE, d_13_tIN, d_14_COM, d_14_OE,
         d_14_tIN, d_15_COM, d_15_OE, d_15_tIN, d_1_COM, d_1_OE, d_1_tIN,
         d_2_COM, d_2_OE, d_2_tIN, d_3_COM, d_3_OE, d_3_tIN, d_4_COM,
         d_4_OE, d_4_tIN, d_5_COM, d_5_OE, d_5_tIN, d_6_COM, d_6_OE,
         d_6_tIN, d_7_COM, d_7_OE, d_7_tIN, d_8_COM, d_8_OE, d_8_tIN,
         d_9_COM, d_9_OE, d_9_tIN, dvm_I_man_data_0_AP,
         dvm_I_man_data_0_AR, dvm_I_man_data_0_D, dvm_I_man_data_0_DIN,
         dvm_I_man_data_0_LE, dvm_I_man_data_0_Q, dvm_I_man_data_0_Q_tF,
         dvm_I_man_data_10_AP, dvm_I_man_data_10_AR, dvm_I_man_data_10_D,
         dvm_I_man_data_10_DIN, dvm_I_man_data_10_LE, dvm_I_man_data_10_Q,
         dvm_I_man_data_10_Q_tF, dvm_I_man_data_11_AP,
         dvm_I_man_data_11_AR, dvm_I_man_data_11_D, dvm_I_man_data_11_DIN,
         dvm_I_man_data_11_LE, dvm_I_man_data_11_Q, dvm_I_man_data_11_Q_tF,
         dvm_I_man_data_12_AP, dvm_I_man_data_12_AR, dvm_I_man_data_12_D,
         dvm_I_man_data_12_DIN, dvm_I_man_data_12_LE, dvm_I_man_data_12_Q,
         dvm_I_man_data_12_Q_tF, dvm_I_man_data_13_AP,
         dvm_I_man_data_13_AR, dvm_I_man_data_13_D, dvm_I_man_data_13_DIN,
         dvm_I_man_data_13_LE, dvm_I_man_data_13_Q, dvm_I_man_data_13_Q_tF,
         dvm_I_man_data_14_AP, dvm_I_man_data_14_AR, dvm_I_man_data_14_D,
         dvm_I_man_data_14_DIN, dvm_I_man_data_14_LE, dvm_I_man_data_14_Q,
         dvm_I_man_data_14_Q_tF, dvm_I_man_data_15_AP,
         dvm_I_man_data_15_AR, dvm_I_man_data_15_D, dvm_I_man_data_15_DIN,
         dvm_I_man_data_15_LE, dvm_I_man_data_15_Q, dvm_I_man_data_15_Q_tF,
         dvm_I_man_data_1_AP, dvm_I_man_data_1_AR, dvm_I_man_data_1_D,
         dvm_I_man_data_1_DIN, dvm_I_man_data_1_LE, dvm_I_man_data_1_Q,
         dvm_I_man_data_1_Q_tF, dvm_I_man_data_2_AP, dvm_I_man_data_2_AR,
         dvm_I_man_data_2_D, dvm_I_man_data_2_DIN, dvm_I_man_data_2_LE,
         dvm_I_man_data_2_Q, dvm_I_man_data_2_Q_tF, dvm_I_man_data_3_AP,
         dvm_I_man_data_3_AR, dvm_I_man_data_3_D, dvm_I_man_data_3_DIN,
         dvm_I_man_data_3_LE, dvm_I_man_data_3_Q, dvm_I_man_data_3_Q_tF,
         dvm_I_man_data_4_AP, dvm_I_man_data_4_AR, dvm_I_man_data_4_D,
         dvm_I_man_data_4_DIN, dvm_I_man_data_4_LE, dvm_I_man_data_4_Q,
         dvm_I_man_data_4_Q_tF, dvm_I_man_data_5_AP, dvm_I_man_data_5_AR,
         dvm_I_man_data_5_D, dvm_I_man_data_5_DIN, dvm_I_man_data_5_LE,
         dvm_I_man_data_5_Q, dvm_I_man_data_5_Q_tF, dvm_I_man_data_6_AP,
         dvm_I_man_data_6_AR, dvm_I_man_data_6_D, dvm_I_man_data_6_DIN,
         dvm_I_man_data_6_LE, dvm_I_man_data_6_Q, dvm_I_man_data_6_Q_tF,
         dvm_I_man_data_7_AP, dvm_I_man_data_7_AR, dvm_I_man_data_7_D,
         dvm_I_man_data_7_DIN, dvm_I_man_data_7_LE, dvm_I_man_data_7_Q,
         dvm_I_man_data_7_Q_tF, dvm_I_man_data_8_AP, dvm_I_man_data_8_AR,
         dvm_I_man_data_8_D, dvm_I_man_data_8_DIN, dvm_I_man_data_8_LE,
         dvm_I_man_data_8_Q, dvm_I_man_data_8_Q_tF, dvm_I_man_data_9_AP,
         dvm_I_man_data_9_AR, dvm_I_man_data_9_D, dvm_I_man_data_9_DIN,
         dvm_I_man_data_9_LE, dvm_I_man_data_9_Q, dvm_I_man_data_9_Q_tF,