top_level.bl3

xilinx reference design for 1553B BUS analyer using

# instance I_462_AND2 
.subckt AND2 I0=N2267 I1=N2948 O=N2951 

# instance I_463_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_6 I1=N2517 O=N2948 

# instance I_465_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N665 O=N2957 

# instance I_466_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_7 I1=N2453 O=N2963 

# instance I_467_AND2 
.subckt AND2 I0=N2267 I1=N2970 O=N2973 

# instance I_468_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_7 I1=N2968 O=N2970 

# instance I_46_AND2 
.subckt AND2 I0=dvm_I_sm_address_5 I1=N855 O=N1020 

# instance I_470_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N668 O=N2979 

# instance I_471_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_8 I1=N2453 O=N2985 

# instance I_472_AND2 
.subckt AND2 I0=N2267 I1=N2993 O=N2996 

# instance I_473_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_8 I1=N2991 O=N2993 

# instance I_475_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N671 O=N3002 

# instance I_476_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_9 I1=N2453 O=N3008 

# instance I_477_AND2 
.subckt AND2 I0=N2267 I1=N3012 O=N3015 

# instance I_478_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_9 I1=N2519 O=N3012 

# instance I_479_AND3 
.subckt AND3 I0=dvm_time_counter_9 I1=dvm_time_counter_8 I2=dvm_time_counter_7 O=N3021 

# instance I_47_AND2 
.subckt AND2 I0=sp_a<7> I1=N733 O=N1025 

# instance I_480_AND3 
.subckt AND3 I0=dvm_time_counter_6 I1=dvm_time_counter_5 I2=dvm_time_counter_4 O=N3026 

# instance I_481_AND2 
.subckt AND2 I0=dvm_time_counter_11 I1=N3044 O=N3047 

# instance I_483_AND2 
.subckt AND2 I0=dvm_time_counter_10 I1=N3036 O=N3042 

# instance I_484_AND3 
.subckt AND3 I0=dvm_time_counter_10 I1=N677 I2=N3036 O=N3052 

# instance I_485_AND2 
.subckt AND2 I0=dvm_time_counter_12 I1=N3060 O=N3063 

# instance I_487_AND3 
.subckt AND3 I0=dvm_time_counter_11 I1=dvm_time_counter_10 I2=N3036 O=N3058 

# instance I_488_AND2 
.subckt AND2 I0=N3036 I1=N3068 O=N3071 

# instance I_489_AND3 
.subckt AND3 I0=dvm_time_counter_11 I1=dvm_time_counter_10 I2=N680 O=N3068 

# instance I_48_AND2 
.subckt AND2 I0=dvm_I_sm_address_6 I1=N855 O=N1029 

# instance I_490_AND3 
.subckt AND3 I0=dvm_time_counter_12 I1=dvm_time_counter_11 I2=dvm_time_counter_10 O=N3077 

# instance I_491_AND2 
.subckt AND2 I0=dvm_time_counter_14 I1=N3088 O=N3091 

# instance I_493_AND2 
.subckt AND2 I0=dvm_time_counter_13 I1=N3080 O=N3086 

# instance I_494_AND3 
.subckt AND3 I0=dvm_time_counter_13 I1=N683 I2=N3080 O=N3096 

# instance I_495_AND2 
.subckt AND2 I0=dvm_time_counter_15 I1=N3104 O=N3107 

# instance I_497_AND3 
.subckt AND3 I0=dvm_time_counter_14 I1=dvm_time_counter_13 I2=N3080 O=N3102 

# instance I_498_AND2 
.subckt AND2 I0=N3080 I1=N3112 O=N3115 

# instance I_499_AND3 
.subckt AND3 I0=dvm_time_counter_14 I1=dvm_time_counter_13 I2=N686 O=N3112 

# instance I_49_AND2 
.subckt AND2 I0=sp_a<8> I1=N733 O=N1034 

# instance I_4_OR4 
.subckt OR4 I0=sp_a<22> I1=sp_a<19> I2=N479 I3=sp_a<20> O=N801 

# instance I_500_AND2 
.subckt AND2 I0=dvm_time_counter_2 I1=N3125 O=N3128 

# instance I_502_AND2 
.subckt AND2 I0=dvm_time_counter_0 I1=dvm_time_counter_1 O=N3123 

# instance I_503_AND3 
.subckt AND3 I0=dvm_time_counter_0 I1=dvm_time_counter_1 I2=N689 O=N3133 

# instance I_504_AND2 
.subckt AND2 I0=dvm_time_counter_3 I1=N3141 O=N3144 

# instance I_506_AND3 
.subckt AND3 I0=dvm_time_counter_2 I1=dvm_time_counter_0 I2=dvm_time_counter_1 O=N3139 

# instance I_507_AND4 
.subckt AND4 I0=dvm_time_counter_2 I1=dvm_time_counter_0 I2=dvm_time_counter_1 I3=N692 O=N3150 

# instance I_508_AND2 
.subckt AND2 I0=dvm_time_counter_5 I1=N3160 O=N3163 

# instance I_50_AND2 
.subckt AND2 I0=dvm_I_sm_address_7 I1=N855 O=N1038 

# instance I_510_AND2 
.subckt AND2 I0=dvm_time_counter_4 I1=N3032 O=N3158 

# instance I_511_AND3 
.subckt AND3 I0=dvm_time_counter_4 I1=N695 I2=N3032 O=N3168 

# instance I_512_AND2 
.subckt AND2 I0=dvm_time_counter_6 I1=N3176 O=N3179 

# instance I_514_AND3 
.subckt AND3 I0=dvm_time_counter_5 I1=dvm_time_counter_4 I2=N3032 O=N3174 

# instance I_515_AND2 
.subckt AND2 I0=N3032 I1=N3184 O=N3187 

# instance I_516_AND3 
.subckt AND3 I0=dvm_time_counter_5 I1=dvm_time_counter_4 I2=N698 O=N3184 

# instance I_517_AND2 
.subckt AND2 I0=dvm_time_counter_8 I1=N3197 O=N3200 

# instance I_519_AND2 
.subckt AND2 I0=dvm_time_counter_7 I1=N3034 O=N3195 

# instance I_51_AND2 
.subckt AND2 I0=sp_a<9> I1=N733 O=N1043 

# instance I_520_AND3 
.subckt AND3 I0=dvm_time_counter_7 I1=N701 I2=N3034 O=N3205 

# instance I_521_AND2 
.subckt AND2 I0=dvm_time_counter_9 I1=N3213 O=N3216 

# instance I_523_AND3 
.subckt AND3 I0=dvm_time_counter_8 I1=dvm_time_counter_7 I2=N3034 O=N3211 

# instance I_524_AND2 
.subckt AND2 I0=N3034 I1=N3221 O=N3224 

# instance I_525_AND3 
.subckt AND3 I0=dvm_time_counter_8 I1=dvm_time_counter_7 I2=N704 O=N3221 

# instance I_526_AND2 
.subckt AND2 I0=sp_d<0> I1=N733 O=N3231 

# instance I_527_AND2 
.subckt AND2 I0=dvm_I_man_data_0 I1=N855 O=N3236 

# instance I_528_AND2 
.subckt AND2 I0=sp_d<10> I1=N733 O=N3242 

# instance I_529_AND2 
.subckt AND2 I0=dvm_I_man_data_10 I1=N855 O=N3247 

# instance I_52_AND2 
.subckt AND2 I0=dvm_I_sm_address_8 I1=N855 O=N1047 

# instance I_530_AND2 
.subckt AND2 I0=sp_d<11> I1=N733 O=N3253 

# instance I_531_AND2 
.subckt AND2 I0=dvm_I_man_data_11 I1=N855 O=N3258 

# instance I_532_AND2 
.subckt AND2 I0=sp_d<12> I1=N733 O=N3264 

# instance I_533_AND2 
.subckt AND2 I0=dvm_I_man_data_12 I1=N855 O=N3269 

# instance I_534_AND2 
.subckt AND2 I0=sp_d<13> I1=N733 O=N3275 

# instance I_535_AND2 
.subckt AND2 I0=dvm_I_man_data_13 I1=N855 O=N3280 

# instance I_536_AND2 
.subckt AND2 I0=sp_d<14> I1=N733 O=N3286 

# instance I_537_AND2 
.subckt AND2 I0=dvm_I_man_data_14 I1=N855 O=N3291 

# instance I_538_AND2 
.subckt AND2 I0=sp_d<15> I1=N733 O=N3297 

# instance I_539_AND2 
.subckt AND2 I0=dvm_I_man_data_15 I1=N855 O=N3302 

# instance I_53_AND2 
.subckt AND2 I0=sp_a<10> I1=N733 O=N1052 

# instance I_540_AND2 
.subckt AND2 I0=sp_d<1> I1=N733 O=N3308 

# instance I_541_AND2 
.subckt AND2 I0=dvm_I_man_data_1 I1=N855 O=N3313 

# instance I_542_AND2 
.subckt AND2 I0=sp_d<2> I1=N733 O=N3319 

# instance I_543_AND2 
.subckt AND2 I0=dvm_I_man_data_2 I1=N855 O=N3324 

# instance I_544_AND2 
.subckt AND2 I0=sp_d<3> I1=N733 O=N3330 

# instance I_545_AND2 
.subckt AND2 I0=dvm_I_man_data_3 I1=N855 O=N3335 

# instance I_546_AND2 
.subckt AND2 I0=sp_d<4> I1=N733 O=N3341 

# instance I_547_AND2 
.subckt AND2 I0=dvm_I_man_data_4 I1=N855 O=N3346 

# instance I_548_AND2 
.subckt AND2 I0=sp_d<5> I1=N733 O=N3352 

# instance I_549_AND2 
.subckt AND2 I0=dvm_I_man_data_5 I1=N855 O=N3357 

# instance I_54_AND2 
.subckt AND2 I0=dvm_I_sm_address_9 I1=N855 O=N1056 

# instance I_550_AND2 
.subckt AND2 I0=sp_d<6> I1=N733 O=N3363 

# instance I_551_AND2 
.subckt AND2 I0=dvm_I_man_data_6 I1=N855 O=N3368 

# instance I_552_AND2 
.subckt AND2 I0=sp_d<7> I1=N733 O=N3374 

# instance I_553_AND2 
.subckt AND2 I0=dvm_I_man_data_7 I1=N855 O=N3379 

# instance I_554_AND2 
.subckt AND2 I0=sp_d<8> I1=N733 O=N3385 

# instance I_555_AND2 
.subckt AND2 I0=dvm_I_man_data_8 I1=N855 O=N3390 

# instance I_556_AND2 
.subckt AND2 I0=sp_d<9> I1=N733 O=N3396 

# instance I_557_AND2 
.subckt AND2 I0=dvm_I_man_data_9 I1=N855 O=N3401 

# instance I_558_AND2 
.subckt AND2 I0=sp_oen I1=N733 O=N3407 

# instance I_559_AND2 
.subckt AND2 I0=dvm_I_statemachine_oe I1=N855 O=N3412 

# instance I_55_AND2 
.subckt AND2 I0=N1118 I1=N1094 O=N1120 

# instance I_560_AND2 
.subckt AND2 I0=sp_wen I1=N733 O=N3418 

# instance I_561_AND2 
.subckt AND2 I0=N3426 I1=N855 O=N3428 

# instance I_562_OR3 
.subckt OR3 I0=N841 I1=N849 I2=N833 O=N3424 

# instance I_563_AND2 
.subckt AND2 I0=sp_cs1n I1=N733 O=N3433 

# instance I_564_AND2 
.subckt AND2 I0=N3426 I1=N855 O=N3437 

# instance I_565_OR2 
.subckt OR2 I0=N3443 I1=sp_oen O=N3445 

# instance I_566_AND2 
.subckt AND2 I0=NET__flash_cs0n I1=sp_cs1n O=N3443 

# instance I_567_AND2 
.subckt AND2 I0=N3454 I1=N3426 O=N3456 

# instance I_568_OR2 
.subckt OR2 I0=N3452 I1=sp_wen O=N3454 

# instance I_569_AND2 
.subckt AND2 I0=NET__flash_cs0n I1=sp_cs1n O=N3452 

# instance I_570_OR2 
.subckt OR2 I0=N1088 I1=N833 O=N3461 

# instance I_571_OR2 
.subckt OR2 I0=N1871 I1=N1895 O=N3466 

# instance I_57_OR3 
.subckt OR3 I0=N1088 I1=N833 I2=N494 O=N1092 

# instance I_58_OR3 
.subckt OR3 I0=N1100 I1=N1114 I2=N1108 O=N1116 

# instance I_59_OR4 
.subckt OR4 I0=dvm_main_curr_state_FFD1 I1=dvm_main_curr_state_FFD3 I2=dvm_main_curr_state_FFD4 I3=dvm_main_curr_state_FFD2 O=N1106 

# instance I_5_AND8 
.subckt AND8 I0=sp_a<2> I1=sp_a<3> I2=sp_a<5> I3=sp_a<18> I4=sp_a<9> I5=sp_a<8> I6=sp_a<15> I7=N482 O=N822 

# instance I_60_AND2 
.subckt AND2 I0=N1125 I1=N494 O=N1127 

# instance I_61_OR2 
.subckt OR2 I0=N1088 I1=N833 O=N1125 

# instance I_62_AND2 
.subckt AND2 I0=dvm_clock_count_1 I1=N1135 O=N1139 

# instance I_63_OR3 
.subckt OR3 I0=N833 I1=N749 I2=N1088 O=N1133 

# instance I_64_AND2 
.subckt AND2 I0=N1144 I1=N735 O=N1146 

# instance I_65_XOR2 
.subckt XOR2 I0=dvm_clock_count_0 I1=dvm_clock_count_1 O=N1144 

# instance I_66_AND2 
.subckt AND2 I0=dvm_clock_count_2 I1=N1135 O=N1151 

# instance I_67_AND2 
.subckt AND2 I0=N1168 I1=N735 O=N1170 

# instance I_68_OR2 
.subckt OR2 I0=N1166 I1=N1157 O=N1168 

# instance I_69_AND2 
.subckt AND2 I0=dvm_clock_count_2 I1=N1163 O=N1166 

# instance I_6_AND2 
.subckt AND2 I0=sp_a<1> I1=N733 O=N827 

# instance I_71_AND2 
.subckt AND2 I0=dvm_clock_count_0 I1=dvm_clock_count_1 O=N1161 

# instance I_72_AND2 
.subckt AND2 I0=dvm_clock_count_3 I1=N1135 O=N1176 

# instance I_73_AND2 
.subckt AND2 I0=N1185 I1=N735 O=N1187 

# instance I_74_XOR2 
.subckt XOR2 I0=N1182 I1=dvm_clock_count_3