top_level.bl3

xilinx reference design for 1553B BUS analyer using

.subckt AND3 I0=dvm_rclock_count_4 I1=N596 I2=N2348 O=N2350 

# instance I_324_OR3 
.subckt OR3 I0=N2367 I1=N2389 I2=N2374 O=N2391 

# instance I_325_AND2 
.subckt AND2 I0=N2257 I1=N2293 O=N2367 

# instance I_327_OR3 
.subckt OR3 I0=dvm_main_curr_state_FFD2 I1=dvm_main_curr_state_FFD4 I2=dvm_main_curr_state_FFD3 O=N2372 

# instance I_328_AND4 
.subckt AND4 I0=dvm_main_curr_state_FFD2 I1=N599 I2=dvm_main_curr_state_FFD3 I3=N2384 O=N2389 

# instance I_32_AND2 
.subckt AND2 I0=dvm_I_sm_address_1 I1=N855 O=N957 

# instance I_330_AND2 
.subckt AND2 I0=N1272 I1=N2379 O=N2382 

# instance I_331_AND3 
.subckt AND3 I0=dvm_main_curr_state_FFD1 I1=dvm_main_curr_state_FFD3 I2=N2410 O=N2412 

# instance I_333_AND3 
.subckt AND3 I0=dvm_main_curr_state_FFD4 I1=N2397 I2=N2406 O=N2408 

# instance I_334_OR2 
.subckt OR2 I0=dvm_data1 I1=dvm_data2 O=N2397 

# instance I_335_AND3 
.subckt AND3 I0=dvm_main_curr_state_FFD2 I1=dvm_clock_count_3 I2=dvm_clock_count_5 O=N2403 

# instance I_336_OR3 
.subckt OR3 I0=N2417 I1=N2433 I2=N2425 O=N2435 

# instance I_337_AND2 
.subckt AND2 I0=dvm_main_curr_state_FFD4 I1=N1342 O=N2417 

# instance I_338_AND2 
.subckt AND2 I0=N2360 I1=N2422 O=N2425 

# instance I_339_AND3 
.subckt AND3 I0=dvm_main_curr_state_FFD1 I1=dvm_mdi1 I2=N587 O=N2422 

# instance I_33_AND2 
.subckt AND2 I0=sp_a<21> I1=N733 O=N962 

# instance I_340_AND2 
.subckt AND2 I0=N2348 I1=N2430 O=N2433 

# instance I_341_AND3 
.subckt AND3 I0=dvm_rclock_count_5 I1=N602 I2=N1342 O=N2430 

# instance I_342_AND2 
.subckt AND2 I0=N2323 I1=N757 O=N2439 

# instance I_344_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N605 O=N2455 

# instance I_346_OR3 
.subckt OR3 I0=dvm_main_curr_state_FFD4 I1=N763 I2=dvm_main_curr_state_FFD2 O=N2449 

# instance I_347_AND2 
.subckt AND2 I0=N2470 I1=N2267 O=N2472 

# instance I_348_OR2 
.subckt OR2 I0=N2468 I1=N2464 O=N2470 

# instance I_34_AND2 
.subckt AND2 I0=dvm_I_sm_address_20 I1=N855 O=N966 

# instance I_350_OR2 
.subckt OR2 I0=dvm_I_sm_address_0 I1=N833 O=N2462 

# instance I_351_AND2 
.subckt AND2 I0=dvm_I_sm_address_0 I1=N833 O=N2468 

# instance I_352_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_0 I1=N2453 O=N2476 

# instance I_354_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N608 O=N2482 

# instance I_355_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_10 I1=N2453 O=N2488 

# instance I_356_AND2 
.subckt AND2 I0=N2267 I1=N2524 O=N2527 

# instance I_357_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_10 I1=N2522 O=N2524 

# instance I_358_AND3 
.subckt AND3 I0=dvm_I_sm_address_8 I1=dvm_I_sm_address_7 I2=dvm_I_sm_address_6 O=N2494 

# instance I_359_AND3 
.subckt AND3 I0=dvm_I_sm_address_5 I1=dvm_I_sm_address_4 I2=dvm_I_sm_address_3 O=N2499 

# instance I_35_AND2 
.subckt AND2 I0=sp_a<22> I1=N733 O=N971 

# instance I_360_OR2 
.subckt OR2 I0=N2510 I1=N2506 O=N2512 

# instance I_361_AND2 
.subckt AND2 I0=N2504 I1=N2283 O=N2506 

# instance I_362_OR2 
.subckt OR2 I0=dvm_I_sm_address_1 I1=N833 O=N2504 

# instance I_363_AND2 
.subckt AND2 I0=dvm_I_sm_address_1 I1=N833 O=N2510 

# instance I_365_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N611 O=N2533 

# instance I_366_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_11 I1=N2453 O=N2539 

# instance I_367_AND2 
.subckt AND2 I0=N2267 I1=N2547 O=N2550 

# instance I_368_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_11 I1=N2545 O=N2547 

# instance I_36_AND2 
.subckt AND2 I0=dvm_I_sm_address_21 I1=N855 O=N975 

# instance I_370_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N614 O=N2556 

# instance I_371_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_12 I1=N2453 O=N2562 

# instance I_372_AND2 
.subckt AND2 I0=N2267 I1=N2573 O=N2576 

# instance I_373_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_12 I1=N2571 O=N2573 

# instance I_374_AND3 
.subckt AND3 I0=dvm_I_sm_address_11 I1=dvm_I_sm_address_10 I2=dvm_I_sm_address_9 O=N2568 

# instance I_376_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N617 O=N2582 

# instance I_377_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_13 I1=N2453 O=N2588 

# instance I_378_AND2 
.subckt AND2 I0=N2267 I1=N2595 O=N2598 

# instance I_379_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_13 I1=N2593 O=N2595 

# instance I_37_AND2 
.subckt AND2 I0=sp_a<23> I1=N733 O=N980 

# instance I_381_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N620 O=N2604 

# instance I_382_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_14 I1=N2453 O=N2610 

# instance I_383_AND2 
.subckt AND2 I0=N2267 I1=N2618 O=N2621 

# instance I_384_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_14 I1=N2616 O=N2618 

# instance I_386_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N623 O=N2627 

# instance I_387_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_15 I1=N2453 O=N2633 

# instance I_388_AND2 
.subckt AND2 I0=N2267 I1=N2644 O=N2647 

# instance I_389_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_15 I1=N2642 O=N2644 

# instance I_38_AND2 
.subckt AND2 I0=dvm_I_sm_address_22 I1=N855 O=N984 

# instance I_390_AND3 
.subckt AND3 I0=dvm_I_sm_address_14 I1=dvm_I_sm_address_13 I2=dvm_I_sm_address_12 O=N2639 

# instance I_392_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N626 O=N2653 

# instance I_393_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_16 I1=N2453 O=N2659 

# instance I_394_AND2 
.subckt AND2 I0=N2267 I1=N2666 O=N2669 

# instance I_395_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_16 I1=N2664 O=N2666 

# instance I_397_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N629 O=N2675 

# instance I_398_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_17 I1=N2453 O=N2681 

# instance I_399_AND2 
.subckt AND2 I0=N2267 I1=N2689 O=N2692 

# instance I_39_AND2 
.subckt AND2 I0=sp_a<3> I1=N733 O=N989 

# instance I_400_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_17 I1=N2687 O=N2689 

# instance I_402_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N632 O=N2698 

# instance I_403_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_18 I1=N2453 O=N2704 

# instance I_404_AND2 
.subckt AND2 I0=N2267 I1=N2715 O=N2718 

# instance I_405_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_18 I1=N2713 O=N2715 

# instance I_406_AND3 
.subckt AND3 I0=dvm_I_sm_address_17 I1=dvm_I_sm_address_16 I2=dvm_I_sm_address_15 O=N2710 

# instance I_408_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N635 O=N2724 

# instance I_409_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_19 I1=N2453 O=N2730 

# instance I_40_AND2 
.subckt AND2 I0=dvm_I_sm_address_2 I1=N855 O=N993 

# instance I_410_AND2 
.subckt AND2 I0=N2267 I1=N2737 O=N2740 

# instance I_411_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_19 I1=N2735 O=N2737 

# instance I_412_AND2 
.subckt AND2 I0=N2744 I1=N2267 O=N2746 

# instance I_413_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_1 I1=N2453 O=N2750 

# instance I_415_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N638 O=N2755 

# instance I_417_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N641 O=N2763 

# instance I_418_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_20 I1=N2453 O=N2769 

# instance I_419_AND2 
.subckt AND2 I0=N2267 I1=N2777 O=N2780 

# instance I_41_AND2 
.subckt AND2 I0=sp_a<4> I1=N733 O=N998 

# instance I_420_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_20 I1=N2775 O=N2777 

# instance I_422_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N644 O=N2786 

# instance I_423_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_21 I1=N2453 O=N2792 

# instance I_424_AND2 
.subckt AND2 I0=N2267 I1=N2803 O=N2806 

# instance I_425_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_21 I1=N2801 O=N2803 

# instance I_426_AND3 
.subckt AND3 I0=dvm_I_sm_address_20 I1=dvm_I_sm_address_19 I2=dvm_I_sm_address_18 O=N2798 

# instance I_428_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N647 O=N2812 

# instance I_429_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_22 I1=N2453 O=N2818 

# instance I_42_AND2 
.subckt AND2 I0=dvm_I_sm_address_3 I1=N855 O=N1002 

# instance I_430_AND2 
.subckt AND2 I0=N2267 I1=N2834 O=N2837 

# instance I_431_OR2 
.subckt OR2 I0=N2832 I1=N2827 O=N2834 

# instance I_432_AND2 
.subckt AND2 I0=dvm_I_sm_address_22 I1=N2824 O=N2827 

# instance I_434_AND2 
.subckt AND2 I0=dvm_I_sm_address_21 I1=N2801 O=N2822 

# instance I_435_AND3 
.subckt AND3 I0=dvm_I_sm_address_21 I1=N647 I2=N2801 O=N2832 

# instance I_437_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N650 O=N2843 

# instance I_438_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_2 I1=N2453 O=N2849 

# instance I_439_AND2 
.subckt AND2 I0=N2267 I1=N2865 O=N2868 

# instance I_43_AND2 
.subckt AND2 I0=sp_a<5> I1=N733 O=N1007 

# instance I_440_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_2 I1=N2863 O=N2865 

# instance I_441_AND2 
.subckt AND2 I0=N2855 I1=N2283 O=N2857 

# instance I_442_OR2 
.subckt OR2 I0=dvm_I_sm_address_1 I1=N833 O=N2855 

# instance I_443_AND2 
.subckt AND2 I0=dvm_I_sm_address_1 I1=N833 O=N2861 

# instance I_445_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N653 O=N2874 

# instance I_446_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_3 I1=N2453 O=N2880 

# instance I_447_AND2 
.subckt AND2 I0=N2267 I1=N2884 O=N2887 

# instance I_448_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_3 I1=N2515 O=N2884 

# instance I_44_AND2 
.subckt AND2 I0=dvm_I_sm_address_4 I1=N855 O=N1011 

# instance I_450_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N656 O=N2893 

# instance I_451_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_4 I1=N2453 O=N2899 

# instance I_452_AND2 
.subckt AND2 I0=N2267 I1=N2906 O=N2909 

# instance I_453_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_4 I1=N2904 O=N2906 

# instance I_455_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N659 O=N2915 

# instance I_456_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_5 I1=N2453 O=N2921 

# instance I_457_AND2 
.subckt AND2 I0=N2267 I1=N2929 O=N2932 

# instance I_458_XOR2 
.subckt XOR2 I0=dvm_I_sm_address_5 I1=N2927 O=N2929 

# instance I_45_AND2 
.subckt AND2 I0=sp_a<6> I1=N733 O=N1016 

# instance I_460_OR3 
.subckt OR3 I0=N2267 I1=N2453 I2=N662 O=N2938 

# instance I_461_AND2 
.subckt AND2 I0=dvm_sram_message_ptr_6 I1=N2453 O=N2944