top_level.bl3

xilinx reference design for 1553B BUS analyer using

# instance dvm_time_counter_5 
.subckt FDCE D=N3170 C=clk16 CLR=NET__test_out CE=N1083 Q=dvm_time_counter_5 

# instance dvm_time_counter_6 
.subckt FDCE D=N3189 C=clk16 CLR=NET__test_out CE=N1083 Q=dvm_time_counter_6 

# instance dvm_time_counter_7 
.subckt FDCE D=N3192 C=clk16 CLR=NET__test_out CE=N1083 Q=dvm_time_counter_7 

# instance dvm_time_counter_8 
.subckt FDCE D=N3207 C=clk16 CLR=NET__test_out CE=N1083 Q=dvm_time_counter_8 

# instance dvm_time_counter_9 
.subckt FDCE D=N3226 C=clk16 CLR=NET__test_out CE=N1083 Q=dvm_time_counter_9 

# instance GND_I 
.subckt GND G=NET__test_out 

# instance I3_I0_I0 
.subckt BUFE I=N3304 E=N3458 O=d<15> 

# instance I3_I10_I0 
.subckt BUFE I=N3359 E=N3458 O=d<5> 

# instance I3_I11_I0 
.subckt BUFE I=N3348 E=N3458 O=d<4> 

# instance I3_I12_I0 
.subckt BUFE I=N3337 E=N3458 O=d<3> 

# instance I3_I13_I0 
.subckt BUFE I=N3326 E=N3458 O=d<2> 

# instance I3_I14_I0 
.subckt BUFE I=N3315 E=N3458 O=d<1> 

# instance I3_I15_I0 
.subckt BUFE I=N3238 E=N3458 O=d<0> 

# instance I3_I1_I0 
.subckt BUFE I=N3293 E=N3458 O=d<14> 

# instance I3_I2_I0 
.subckt BUFE I=N3282 E=N3458 O=d<13> 

# instance I3_I3_I0 
.subckt BUFE I=N3271 E=N3458 O=d<12> 

# instance I3_I4_I0 
.subckt BUFE I=N3260 E=N3458 O=d<11> 

# instance I3_I5_I0 
.subckt BUFE I=N3249 E=N3458 O=d<10> 

# instance I3_I6_I0 
.subckt BUFE I=N3403 E=N3458 O=d<9> 

# instance I3_I7_I0 
.subckt BUFE I=N3392 E=N3458 O=d<8> 

# instance I3_I8_I0 
.subckt BUFE I=N3381 E=N3458 O=d<7> 

# instance I3_I9_I0 
.subckt BUFE I=N3370 E=N3458 O=d<6> 

# instance I4_I0_I0 
.subckt BUFE I=d<15> E=N3447 O=sp_d<15> 

# instance I4_I10_I0 
.subckt BUFE I=d<5> E=N3447 O=sp_d<5> 

# instance I4_I11_I0 
.subckt BUFE I=d<4> E=N3447 O=sp_d<4> 

# instance I4_I12_I0 
.subckt BUFE I=d<3> E=N3447 O=sp_d<3> 

# instance I4_I13_I0 
.subckt BUFE I=d<2> E=N3447 O=sp_d<2> 

# instance I4_I14_I0 
.subckt BUFE I=d<1> E=N3447 O=sp_d<1> 

# instance I4_I15_I0 
.subckt BUFE I=d<0> E=N3447 O=sp_d<0> 

# instance I4_I1_I0 
.subckt BUFE I=d<14> E=N3447 O=sp_d<14> 

# instance I4_I2_I0 
.subckt BUFE I=d<13> E=N3447 O=sp_d<13> 

# instance I4_I3_I0 
.subckt BUFE I=d<12> E=N3447 O=sp_d<12> 

# instance I4_I4_I0 
.subckt BUFE I=d<11> E=N3447 O=sp_d<11> 

# instance I4_I5_I0 
.subckt BUFE I=d<10> E=N3447 O=sp_d<10> 

# instance I4_I6_I0 
.subckt BUFE I=d<9> E=N3447 O=sp_d<9> 

# instance I4_I7_I0 
.subckt BUFE I=d<8> E=N3447 O=sp_d<8> 

# instance I4_I8_I0 
.subckt BUFE I=d<7> E=N3447 O=sp_d<7> 

# instance I4_I9_I0 
.subckt BUFE I=d<6> E=N3447 O=sp_d<6> 

# instance I_0_AND3 
.subckt AND3 I0=N792 I1=N784 I2=N803 O=N805 

# instance I_100_AND2 
.subckt AND2 I0=dvm_pwclock_count_4 I1=N1305 O=N1308 

# instance I_102_AND2 
.subckt AND2 I0=dvm_pwclock_count_3 I1=N1289 O=N1303 

# instance I_103_AND3 
.subckt AND3 I0=dvm_pwclock_count_3 I1=N503 I2=N1289 O=N1313 

# instance I_104_AND2 
.subckt AND2 I0=dvm_rclock_count_0 I1=N1351 O=N1354 

# instance I_106_OR3 
.subckt OR3 I0=N1108 I1=N849 I2=N1088 O=N1324 

# instance I_107_OR3 
.subckt OR3 I0=N1334 I1=N1345 I2=N1114 O=N1347 

# instance I_108_OR4 
.subckt OR4 I0=dvm_main_curr_state_FFD1 I1=dvm_main_curr_state_FFD3 I2=N581 I3=dvm_main_curr_state_FFD4 O=N1332 

# instance I_109_AND2 
.subckt AND2 I0=dvm_main_curr_state_FFD4 I1=N1342 O=N1345 

# instance I_10_OR4 
.subckt OR4 I0=dvm_main_curr_state_FFD1 I1=dvm_main_curr_state_FFD3 I2=N599 I3=dvm_main_curr_state_FFD2 O=N847 

# instance I_110_OR3 
.subckt OR3 I0=dvm_main_curr_state_FFD1 I1=dvm_main_curr_state_FFD3 I2=N581 O=N1340 

# instance I_112_OR2 
.subckt OR2 I0=dvm_rclock_count_0 I1=N1349 O=N1358 

# instance I_113_AND2 
.subckt AND2 I0=dvm_rclock_count_1 I1=N1351 O=N1365 

# instance I_114_AND2 
.subckt AND2 I0=N1370 I1=N737 O=N1372 

# instance I_115_XOR2 
.subckt XOR2 I0=dvm_rclock_count_0 I1=dvm_rclock_count_1 O=N1370 

# instance I_116_AND2 
.subckt AND2 I0=dvm_rclock_count_2 I1=N1351 O=N1377 

# instance I_117_AND2 
.subckt AND2 I0=N1385 I1=N737 O=N1387 

# instance I_118_XOR2 
.subckt XOR2 I0=dvm_rclock_count_2 I1=N1383 O=N1385 

# instance I_119_AND2 
.subckt AND2 I0=dvm_rclock_count_3 I1=N1351 O=N1392 

# instance I_11_AND2 
.subckt AND2 I0=sp_a<11> I1=N733 O=N863 

# instance I_120_AND2 
.subckt AND2 I0=N1401 I1=N737 O=N1403 

# instance I_121_XOR2 
.subckt XOR2 I0=N1398 I1=dvm_rclock_count_3 O=N1401 

# instance I_122_AND2 
.subckt AND2 I0=dvm_rclock_count_4 I1=N1351 O=N1408 

# instance I_123_AND2 
.subckt AND2 I0=N1418 I1=N737 O=N1420 

# instance I_124_XOR2 
.subckt XOR2 I0=N1415 I1=dvm_rclock_count_4 O=N1418 

# instance I_125_AND2 
.subckt AND2 I0=dvm_rclock_count_5 I1=N1351 O=N1425 

# instance I_126_AND2 
.subckt AND2 I0=N1433 I1=N737 O=N1435 

# instance I_127_XOR2 
.subckt XOR2 I0=N1430 I1=dvm_rclock_count_5 O=N1433 

# instance I_128_AND2 
.subckt AND2 I0=dvm_rclock_count_6 I1=N1351 O=N1441 

# instance I_129_AND2 
.subckt AND2 I0=N1450 I1=N737 O=N1452 

# instance I_12_AND2 
.subckt AND2 I0=dvm_I_sm_address_10 I1=N855 O=N867 

# instance I_130_XOR2 
.subckt XOR2 I0=N1447 I1=dvm_rclock_count_6 O=N1450 

# instance I_131_AND2 
.subckt AND2 I0=dvm_rclock_count_7 I1=N1351 O=N1457 

# instance I_132_AND2 
.subckt AND2 I0=N1474 I1=N737 O=N1476 

# instance I_133_OR2 
.subckt OR2 I0=N1472 I1=N1467 O=N1474 

# instance I_134_AND2 
.subckt AND2 I0=dvm_rclock_count_7 I1=N1464 O=N1467 

# instance I_136_AND2 
.subckt AND2 I0=dvm_rclock_count_6 I1=N1447 O=N1462 

# instance I_137_AND3 
.subckt AND3 I0=dvm_rclock_count_6 I1=N506 I2=N1447 O=N1472 

# instance I_138_AND3 
.subckt AND3 I0=dvm_clock_count_4 I1=dvm_clock_count_3 I2=N497 O=N1482 

# instance I_139_AND3 
.subckt AND3 I0=dvm_clock_count_0 I1=dvm_clock_count_1 I2=N509 O=N1488 

# instance I_13_AND2 
.subckt AND2 I0=sp_a<12> I1=N733 O=N872 

# instance I_141_OR3 
.subckt OR3 I0=dvm_clock_count_3 I1=dvm_clock_count_4 I2=N497 O=N1494 

# instance I_142_AND2 
.subckt AND2 I0=dvm_data3 I1=N1528 O=N1532 

# instance I_143_OR3 
.subckt OR3 I0=N1518 I1=N1526 I2=N1522 O=N1528 

# instance I_145_OR2 
.subckt OR2 I0=N1514 I1=N1508 O=N1516 

# instance I_146_OR2 
.subckt OR2 I0=N1504 I1=N1334 O=N1506 

# instance I_147_AND2 
.subckt AND2 I0=dvm_main_curr_state_FFD4 I1=N1342 O=N1504 

# instance I_148_AND2 
.subckt AND2 I0=N1508 I1=N739 O=N1522 

# instance I_149_AND2 
.subckt AND2 I0=N1239 I1=N741 O=N1526 

# instance I_14_AND2 
.subckt AND2 I0=dvm_I_sm_address_11 I1=N855 O=N876 

# instance I_150_AND2 
.subckt AND2 I0=dvm_mdi1 I1=N1547 O=N1550 

# instance I_151_OR2 
.subckt OR2 I0=N1545 I1=N1536 O=N1547 

# instance I_152_AND2 
.subckt AND2 I0=N1514 I1=N743 O=N1536 

# instance I_153_AND2 
.subckt AND2 I0=N1239 I1=N1542 O=N1545 

# instance I_155_OR3 
.subckt OR3 I0=N1108 I1=N841 I2=N512 O=N1556 

# instance I_156_AND2 
.subckt AND2 I0=N1561 I1=N841 O=N1563 

# instance I_158_OR3 
.subckt OR3 I0=N1108 I1=N841 I2=N515 O=N1569 

# instance I_159_AND2 
.subckt AND2 I0=N1574 I1=N841 O=N1576 

# instance I_15_AND2 
.subckt AND2 I0=sp_a<13> I1=N733 O=N881 

# instance I_161_OR3 
.subckt OR3 I0=N1108 I1=N841 I2=N518 O=N1582 

# instance I_162_AND2 
.subckt AND2 I0=N1587 I1=N841 O=N1589 

# instance I_164_OR3 
.subckt OR3 I0=N1108 I1=N841 I2=N521 O=N1595 

# instance I_165_AND2 
.subckt AND2 I0=N1600 I1=N841 O=N1602 

# instance I_167_OR3 
.subckt OR3 I0=N1108 I1=N841 I2=N524 O=N1608 

# instance I_168_AND2 
.subckt AND2 I0=N1613 I1=N841 O=N1615 

# instance I_16_AND2 
.subckt AND2 I0=dvm_I_sm_address_12 I1=N855 O=N885 

# instance I_170_OR3 
.subckt OR3 I0=N1108 I1=N841 I2=N527 O=N1621 

# instance I_171_AND2 
.subckt AND2 I0=N1626 I1=N841 O=N1628 

# instance I_173_OR3 
.subckt OR3 I0=N1108 I1=N841 I2=N530 O=N1634 

# instance I_174_AND2 
.subckt AND2 I0=N1639 I1=N841 O=N1641 

# instance I_176_OR3 
.subckt OR3 I0=N1108 I1=N841 I2=N533 O=N1647 

# instance I_177_AND2 
.subckt AND2 I0=N1652 I1=N841 O=N1654 

# instance I_179_OR3 
.subckt OR3 I0=N1108 I1=N841 I2=N536 O=N1660 

# instance I_17_AND2 
.subckt AND2 I0=sp_a<14> I1=N733 O=N890 

# instance I_180_AND2 
.subckt AND2 I0=N1665 I1=N841 O=N1667 

# instance I_182_OR3 
.subckt OR3 I0=N1108 I1=N841 I2=N539 O=N1673 

# instance I_183_AND2 
.subckt AND2 I0=N1678 I1=N841 O=N1680 

# instance I_185_OR3 
.subckt OR3 I0=N1108 I1=N841 I2=N542 O=N1686 

# instance I_186_AND2 
.subckt AND2 I0=N1691 I1=N841 O=N1693 

# instance I_188_OR3 
.subckt OR3 I0=N1108 I1=N841 I2=N545 O=N1699 

# instance I_189_AND2 
.subckt AND2 I0=N1704 I1=N841 O=N1706 

# instance I_18_AND2 
.subckt AND2 I0=dvm_I_sm_address_13 I1=N855 O=N894 

# instance I_191_OR3 
.subckt OR3 I0=N1108 I1=N841 I2=N548 O=N1712 

# instance I_192_AND2 
.subckt AND2 I0=N1717 I1=N841 O=N1719 

# instance I_194_OR3 
.subckt OR3 I0=N1108 I1=N841 I2=N551 O=N1725 

# instance I_195_AND2 
.subckt AND2 I0=N1730 I1=N841 O=N1732 

# instance I_197_OR3 
.subckt OR3 I0=N1108 I1=N841 I2=N554 O=N1738 

# instance I_198_AND2 
.subckt AND2 I0=N1743 I1=N841 O=N1745 

# instance I_19_AND2 
.subckt AND2 I0=sp_a<15> I1=N733 O=N899