updncnt.tan.rpt

universal count un iversal count

; Slack ; Required tco ; Actual tco ; From     ; To   ; From Clock ;
+-------+--------------+------------+----------+------+------------+
; N/A   ; None         ; 6.096 ns   ; q_int[1] ; q[1] ; clk        ;
; N/A   ; None         ; 6.089 ns   ; q_int[2] ; q[2] ; clk        ;
; N/A   ; None         ; 6.078 ns   ; q_int[3] ; q[3] ; clk        ;
; N/A   ; None         ; 6.066 ns   ; q_int[0] ; q[0] ; clk        ;
+-------+--------------+------------+----------+------+------------+


+-----------------------------------------------------------+
; tpd                                                       ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To   ;
+-------+-------------------+-----------------+------+------+
; N/A   ; None              ; 5.244 ns        ; en   ; q[1] ;
; N/A   ; None              ; 5.224 ns        ; en   ; q[3] ;
; N/A   ; None              ; 5.224 ns        ; en   ; q[2] ;
; N/A   ; None              ; 5.214 ns        ; en   ; q[0] ;
+-------+-------------------+-----------------+------+------+


+----------------------------------------------------------------------+
; th                                                                   ;
+---------------+-------------+-----------+------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To       ; To Clock ;
+---------------+-------------+-----------+------+----------+----------+
; N/A           ; None        ; -0.441 ns ; d[0] ; q_int[0] ; clk      ;
; N/A           ; None        ; -2.934 ns ; d[1] ; q_int[1] ; clk      ;
; N/A           ; None        ; -2.957 ns ; d[2] ; q_int[2] ; clk      ;
; N/A           ; None        ; -3.166 ns ; clr  ; q_int[3] ; clk      ;
; N/A           ; None        ; -3.168 ns ; clr  ; q_int[1] ; clk      ;
; N/A           ; None        ; -3.186 ns ; d[3] ; q_int[3] ; clk      ;
; N/A           ; None        ; -3.309 ns ; clr  ; q_int[0] ; clk      ;
; N/A           ; None        ; -3.310 ns ; clr  ; q_int[2] ; clk      ;
; N/A           ; None        ; -3.329 ns ; dn   ; q_int[3] ; clk      ;
; N/A           ; None        ; -3.330 ns ; dn   ; q_int[0] ; clk      ;
; N/A           ; None        ; -3.330 ns ; dn   ; q_int[2] ; clk      ;
; N/A           ; None        ; -3.359 ns ; up   ; q_int[3] ; clk      ;
; N/A           ; None        ; -3.360 ns ; up   ; q_int[0] ; clk      ;
; N/A           ; None        ; -3.360 ns ; up   ; q_int[2] ; clk      ;
; N/A           ; None        ; -3.424 ns ; q[0] ; q_int[0] ; clk      ;
; N/A           ; None        ; -3.451 ns ; ld   ; q_int[3] ; clk      ;
; N/A           ; None        ; -3.452 ns ; ld   ; q_int[0] ; clk      ;
; N/A           ; None        ; -3.452 ns ; ld   ; q_int[2] ; clk      ;
; N/A           ; None        ; -3.593 ns ; q[1] ; q_int[1] ; clk      ;
; N/A           ; None        ; -3.595 ns ; q[3] ; q_int[3] ; clk      ;
; N/A           ; None        ; -3.639 ns ; dn   ; q_int[1] ; clk      ;
; N/A           ; None        ; -3.653 ns ; q[2] ; q_int[2] ; clk      ;
; N/A           ; None        ; -3.669 ns ; up   ; q_int[1] ; clk      ;
; N/A           ; None        ; -3.761 ns ; ld   ; q_int[1] ; clk      ;
; N/A           ; None        ; -4.479 ns ; q[0] ; q_int[1] ; clk      ;
; N/A           ; None        ; -4.532 ns ; q[2] ; q_int[3] ; clk      ;
; N/A           ; None        ; -4.624 ns ; q[0] ; q_int[3] ; clk      ;
; N/A           ; None        ; -4.742 ns ; q[0] ; q_int[2] ; clk      ;
; N/A           ; None        ; -4.832 ns ; q[1] ; q_int[3] ; clk      ;
; N/A           ; None        ; -4.950 ns ; q[1] ; q_int[2] ; clk      ;
+---------------+-------------+-----------+------+----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Mon Jan 21 20:45:05 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off UpDnCnt -c UpDnCnt --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clk"
Info: tsu for register "q_int[2]" (data pin = "ld", clock pin = "clk") is 5.729 ns
    Info: + Longest pin to register delay is 8.435 ns
        Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_H6; Fanout = 4; PIN Node = 'ld'
        Info: 2: + IC(4.782 ns) + CELL(0.275 ns) = 5.889 ns; Loc. = LCCOMB_X1_Y32_N2; Fanout = 5; COMB Node = 'always0~48'
        Info: 3: + IC(0.267 ns) + CELL(0.393 ns) = 6.549 ns; Loc. = LCCOMB_X1_Y32_N20; Fanout = 2; COMB Node = 'Add0~731'
        Info: 4: + IC(0.000 ns) + CELL(0.410 ns) = 6.959 ns; Loc. = LCCOMB_X1_Y32_N22; Fanout = 1; COMB Node = 'Add0~734'
        Info: 5: + IC(0.259 ns) + CELL(0.420 ns) = 7.638 ns; Loc. = LCCOMB_X1_Y32_N10; Fanout = 1; COMB Node = 'Add0~736'
        Info: 6: + IC(0.275 ns) + CELL(0.438 ns) = 8.351 ns; Loc. = LCCOMB_X1_Y32_N14; Fanout = 1; COMB Node = 'Add0~737'
        Info: 7: + IC(0.000 ns) + CELL(0.084 ns) = 8.435 ns; Loc. = LCFF_X1_Y32_N15; Fanout = 1; REG Node = 'q_int[2]'
        Info: Total cell delay = 2.852 ns ( 33.81 % )
        Info: Total interconnect delay = 5.583 ns ( 66.19 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.670 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.016 ns) + CELL(0.537 ns) = 2.670 ns; Loc. = LCFF_X1_Y32_N15; Fanout = 1; REG Node = 'q_int[2]'
        Info: Total cell delay = 1.536 ns ( 57.53 % )
        Info: Total interconnect delay = 1.134 ns ( 42.47 % )
Info: tco from clock "clk" to destination pin "q[1]" through register "q_int[1]" is 6.096 ns
    Info: + Longest clock path from clock "clk" to source register is 2.670 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.016 ns) + CELL(0.537 ns) = 2.670 ns; Loc. = LCFF_X1_Y32_N29; Fanout = 1; REG Node = 'q_int[1]'
        Info: Total cell delay = 1.536 ns ( 57.53 % )
        Info: Total interconnect delay = 1.134 ns ( 42.47 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.176 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y32_N29; Fanout = 1; REG Node = 'q_int[1]'
        Info: 2: + IC(0.514 ns) + CELL(2.662 ns) = 3.176 ns; Loc. = PIN_D2; Fanout = 0; PIN Node = 'q[1]'
        Info: Total cell delay = 2.662 ns ( 83.82 % )
        Info: Total interconnect delay = 0.514 ns ( 16.18 % )
Info: Longest tpd from source pin "en" to destination pin "q[1]" is 5.244 ns
    Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 4; PIN Node = 'en'
    Info: 2: + IC(1.573 ns) + CELL(2.692 ns) = 5.244 ns; Loc. = PIN_D2; Fanout = 0; PIN Node = 'q[1]'
    Info: Total cell delay = 3.671 ns ( 70.00 % )
    Info: Total interconnect delay = 1.573 ns ( 30.00 % )
Info: th for register "q_int[0]" (data pin = "d[0]", clock pin = "clk") is -0.441 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.670 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.016 ns) + CELL(0.537 ns) = 2.670 ns; Loc. = LCFF_X1_Y32_N13; Fanout = 1; REG Node = 'q_int[0]'
        Info: Total cell delay = 1.536 ns ( 57.53 % )
        Info: Total interconnect delay = 1.134 ns ( 42.47 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 3.377 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 1; PIN Node = 'd[0]'
        Info: 2: + IC(2.043 ns) + CELL(0.271 ns) = 3.293 ns; Loc. = LCCOMB_X1_Y32_N12; Fanout = 1; COMB Node = 'q_int~396'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 3.377 ns; Loc. = LCFF_X1_Y32_N13; Fanout = 1; REG Node = 'q_int[0]'
        Info: Total cell delay = 1.334 ns ( 39.50 % )
        Info: Total interconnect delay = 2.043 ns ( 60.50 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 109 megabytes of memory during processing
    Info: Processing ended: Mon Jan 21 20:45:24 2008
    Info: Elapsed time: 00:00:19