updncnt.tan.rpt

universal count un iversal count

Classic Timing Analyzer report for UpDnCnt
Mon Jan 21 20:45:24 2008
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. tsu
  6. tco
  7. tpd
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                         ;
+------------------------------+-------+---------------+-------------+----------+----------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From     ; To       ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+----------+----------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 5.729 ns    ; ld       ; q_int[2] ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 6.096 ns    ; q_int[1] ; q[1]     ; clk        ; --       ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 5.244 ns    ; en       ; q[1]     ; --         ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -0.441 ns   ; d[0]     ; q_int[0] ; --         ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;             ;          ;          ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+----------+----------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------+
; tsu                                                            ;
+-------+--------------+------------+------+----------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To       ; To Clock ;
+-------+--------------+------------+------+----------+----------+
; N/A   ; None         ; 5.729 ns   ; ld   ; q_int[2] ; clk      ;
; N/A   ; None         ; 5.677 ns   ; up   ; q_int[2] ; clk      ;
; N/A   ; None         ; 5.611 ns   ; ld   ; q_int[3] ; clk      ;
; N/A   ; None         ; 5.608 ns   ; dn   ; q_int[2] ; clk      ;
; N/A   ; None         ; 5.559 ns   ; up   ; q_int[3] ; clk      ;
; N/A   ; None         ; 5.490 ns   ; dn   ; q_int[3] ; clk      ;
; N/A   ; None         ; 5.180 ns   ; q[1] ; q_int[2] ; clk      ;
; N/A   ; None         ; 5.154 ns   ; ld   ; q_int[1] ; clk      ;
; N/A   ; None         ; 5.102 ns   ; up   ; q_int[1] ; clk      ;
; N/A   ; None         ; 5.062 ns   ; q[1] ; q_int[3] ; clk      ;
; N/A   ; None         ; 5.033 ns   ; dn   ; q_int[1] ; clk      ;
; N/A   ; None         ; 4.972 ns   ; q[0] ; q_int[2] ; clk      ;
; N/A   ; None         ; 4.854 ns   ; q[0] ; q_int[3] ; clk      ;
; N/A   ; None         ; 4.762 ns   ; q[2] ; q_int[3] ; clk      ;
; N/A   ; None         ; 4.709 ns   ; q[0] ; q_int[1] ; clk      ;
; N/A   ; None         ; 4.600 ns   ; q[1] ; q_int[1] ; clk      ;
; N/A   ; None         ; 4.565 ns   ; q[2] ; q_int[2] ; clk      ;
; N/A   ; None         ; 4.351 ns   ; q[3] ; q_int[3] ; clk      ;
; N/A   ; None         ; 4.119 ns   ; ld   ; q_int[0] ; clk      ;
; N/A   ; None         ; 3.915 ns   ; up   ; q_int[0] ; clk      ;
; N/A   ; None         ; 3.856 ns   ; dn   ; q_int[0] ; clk      ;
; N/A   ; None         ; 3.654 ns   ; q[0] ; q_int[0] ; clk      ;
; N/A   ; None         ; 3.540 ns   ; clr  ; q_int[2] ; clk      ;
; N/A   ; None         ; 3.539 ns   ; clr  ; q_int[0] ; clk      ;
; N/A   ; None         ; 3.416 ns   ; d[3] ; q_int[3] ; clk      ;
; N/A   ; None         ; 3.398 ns   ; clr  ; q_int[1] ; clk      ;
; N/A   ; None         ; 3.396 ns   ; clr  ; q_int[3] ; clk      ;
; N/A   ; None         ; 3.187 ns   ; d[2] ; q_int[2] ; clk      ;
; N/A   ; None         ; 3.164 ns   ; d[1] ; q_int[1] ; clk      ;
; N/A   ; None         ; 0.671 ns   ; d[0] ; q_int[0] ; clk      ;
+-------+--------------+------------+------+----------+----------+


+------------------------------------------------------------------+
; tco                                                              ;
+-------+--------------+------------+----------+------+------------+