updncnt.map.qmsg

universal count un iversal count

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 21 20:43:16 2008 " "Info: Processing started: Mon Jan 21 20:43:16 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off UpDnCnt -c UpDnCnt " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UpDnCnt -c UpDnCnt" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "UpDnCnt_tb.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file UpDnCnt_tb.v" { { "Info" "ISGN_ENTITY_NAME" "1 UpDnCnt_tb " "Info: Found entity 1: UpDnCnt_tb" {  } { { "UpDnCnt_tb.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt_tb.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "UpDnCnt.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file UpDnCnt.v" { { "Info" "ISGN_ENTITY_NAME" "1 UpDnCnt " "Info: Found entity 1: UpDnCnt" {  } { { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "UpDnCnt " "Info: Elaborating entity \"UpDnCnt\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 UpDnCnt.v(18) " "Warning (10230): Verilog HDL assignment warning at UpDnCnt.v(18): truncated value with size 32 to match size of target (4)" {  } { { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 18 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 UpDnCnt.v(21) " "Warning (10230): Verilog HDL assignment warning at UpDnCnt.v(21): truncated value with size 32 to match size of target (4)" {  } { { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 21 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "33 " "Info: Implemented 33 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "0 " "Info: Implemented 0 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "15 " "Info: Implemented 15 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "125 " "Info: Allocated 125 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 21 20:43:36 2008 " "Info: Processing ended: Mon Jan 21 20:43:36 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:20 " "Info: Elapsed time: 00:00:20" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}