updncnt.tan.qmsg

universal count un iversal count

{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[1\] q_int\[1\] 6.096 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[1\]\" through register \"q_int\[1\]\" is 6.096 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.670 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 1 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 4 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 1 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.016 ns) + CELL(0.537 ns) 2.670 ns q_int\[1\] 3 REG LCFF_X1_Y32_N29 1 " "Info: 3: + IC(1.016 ns) + CELL(0.537 ns) = 2.670 ns; Loc. = LCFF_X1_Y32_N29; Fanout = 1; REG Node = 'q_int\[1\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.553 ns" { clk~clkctrl q_int[1] } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.53 % ) " "Info: Total cell delay = 1.536 ns ( 57.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.134 ns ( 42.47 % ) " "Info: Total interconnect delay = 1.134 ns ( 42.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.670 ns" { clk clk~clkctrl q_int[1] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.670 ns" { clk clk~combout clk~clkctrl q_int[1] } { 0.000ns 0.000ns 0.118ns 1.016ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 10 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.176 ns + Longest register pin " "Info: + Longest register to pin delay is 3.176 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q_int\[1\] 1 REG LCFF_X1_Y32_N29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y32_N29; Fanout = 1; REG Node = 'q_int\[1\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { q_int[1] } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.514 ns) + CELL(2.662 ns) 3.176 ns q\[1\] 2 PIN PIN_D2 0 " "Info: 2: + IC(0.514 ns) + CELL(2.662 ns) = 3.176 ns; Loc. = PIN_D2; Fanout = 0; PIN Node = 'q\[1\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.176 ns" { q_int[1] q[1] } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.662 ns ( 83.82 % ) " "Info: Total cell delay = 2.662 ns ( 83.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.514 ns ( 16.18 % ) " "Info: Total interconnect delay = 0.514 ns ( 16.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.176 ns" { q_int[1] q[1] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.176 ns" { q_int[1] q[1] } { 0.000ns 0.514ns } { 0.000ns 2.662ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.670 ns" { clk clk~clkctrl q_int[1] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.670 ns" { clk clk~combout clk~clkctrl q_int[1] } { 0.000ns 0.000ns 0.118ns 1.016ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.176 ns" { q_int[1] q[1] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.176 ns" { q_int[1] q[1] } { 0.000ns 0.514ns } { 0.000ns 2.662ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "en q\[1\] 5.244 ns Longest " "Info: Longest tpd from source pin \"en\" to destination pin \"q\[1\]\" is 5.244 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns en 1 PIN PIN_C13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 4; PIN Node = 'en'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 1 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.573 ns) + CELL(2.692 ns) 5.244 ns q\[1\] 2 PIN PIN_D2 0 " "Info: 2: + IC(1.573 ns) + CELL(2.692 ns) = 5.244 ns; Loc. = PIN_D2; Fanout = 0; PIN Node = 'q\[1\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.265 ns" { en q[1] } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.671 ns ( 70.00 % ) " "Info: Total cell delay = 3.671 ns ( 70.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.573 ns ( 30.00 % ) " "Info: Total interconnect delay = 1.573 ns ( 30.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.244 ns" { en q[1] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.244 ns" { en en~combout q[1] } { 0.000ns 0.000ns 1.573ns } { 0.000ns 0.979ns 2.692ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "q_int\[0\] d\[0\] clk -0.441 ns register " "Info: th for register \"q_int\[0\]\" (data pin = \"d\[0\]\", clock pin = \"clk\") is -0.441 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.670 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 1 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 4 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 1 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.016 ns) + CELL(0.537 ns) 2.670 ns q_int\[0\] 3 REG LCFF_X1_Y32_N13 1 " "Info: 3: + IC(1.016 ns) + CELL(0.537 ns) = 2.670 ns; Loc. = LCFF_X1_Y32_N13; Fanout = 1; REG Node = 'q_int\[0\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.553 ns" { clk~clkctrl q_int[0] } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.53 % ) " "Info: Total cell delay = 1.536 ns ( 57.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.134 ns ( 42.47 % ) " "Info: Total interconnect delay = 1.134 ns ( 42.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.670 ns" { clk clk~clkctrl q_int[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.670 ns" { clk clk~combout clk~clkctrl q_int[0] } { 0.000ns 0.000ns 0.118ns 1.016ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 10 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.377 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.377 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns d\[0\] 1 PIN PIN_D13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 1; PIN Node = 'd\[0\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { d[0] } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.043 ns) + CELL(0.271 ns) 3.293 ns q_int~396 2 COMB LCCOMB_X1_Y32_N12 1 " "Info: 2: + IC(2.043 ns) + CELL(0.271 ns) = 3.293 ns; Loc. = LCCOMB_X1_Y32_N12; Fanout = 1; COMB Node = 'q_int~396'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.314 ns" { d[0] q_int~396 } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.377 ns q_int\[0\] 3 REG LCFF_X1_Y32_N13 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 3.377 ns; Loc. = LCFF_X1_Y32_N13; Fanout = 1; REG Node = 'q_int\[0\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { q_int~396 q_int[0] } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.334 ns ( 39.50 % ) " "Info: Total cell delay = 1.334 ns ( 39.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.043 ns ( 60.50 % ) " "Info: Total interconnect delay = 2.043 ns ( 60.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.377 ns" { d[0] q_int~396 q_int[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.377 ns" { d[0] d[0]~combout q_int~396 q_int[0] } { 0.000ns 0.000ns 2.043ns 0.000ns } { 0.000ns 0.979ns 0.271ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.670 ns" { clk clk~clkctrl q_int[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.670 ns" { clk clk~combout clk~clkctrl q_int[0] } { 0.000ns 0.000ns 0.118ns 1.016ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.377 ns" { d[0] q_int~396 q_int[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.377 ns" { d[0] d[0]~combout q_int~396 q_int[0] } { 0.000ns 0.000ns 2.043ns 0.000ns } { 0.000ns 0.979ns 0.271ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "109 " "Info: Allocated 109 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 21 20:45:24 2008 " "Info: Processing ended: Mon Jan 21 20:45:24 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Info: Elapsed time: 00:00:19" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}