updncnt.tan.qmsg

universal count un iversal count

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 21 20:45:05 2008 " "Info: Processing started: Mon Jan 21 20:45:05 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off UpDnCnt -c UpDnCnt --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off UpDnCnt -c UpDnCnt --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 1 -1 0 } } { "c:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "q_int\[2\] ld clk 5.729 ns register " "Info: tsu for register \"q_int\[2\]\" (data pin = \"ld\", clock pin = \"clk\") is 5.729 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.435 ns + Longest pin register " "Info: + Longest pin to register delay is 8.435 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.832 ns) 0.832 ns ld 1 PIN PIN_H6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_H6; Fanout = 4; PIN Node = 'ld'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { ld } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 1 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.782 ns) + CELL(0.275 ns) 5.889 ns always0~48 2 COMB LCCOMB_X1_Y32_N2 5 " "Info: 2: + IC(4.782 ns) + CELL(0.275 ns) = 5.889 ns; Loc. = LCCOMB_X1_Y32_N2; Fanout = 5; COMB Node = 'always0~48'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.057 ns" { ld always0~48 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.267 ns) + CELL(0.393 ns) 6.549 ns Add0~731 3 COMB LCCOMB_X1_Y32_N20 2 " "Info: 3: + IC(0.267 ns) + CELL(0.393 ns) = 6.549 ns; Loc. = LCCOMB_X1_Y32_N20; Fanout = 2; COMB Node = 'Add0~731'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.660 ns" { always0~48 Add0~731 } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 6.959 ns Add0~734 4 COMB LCCOMB_X1_Y32_N22 1 " "Info: 4: + IC(0.000 ns) + CELL(0.410 ns) = 6.959 ns; Loc. = LCCOMB_X1_Y32_N22; Fanout = 1; COMB Node = 'Add0~734'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { Add0~731 Add0~734 } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(0.420 ns) 7.638 ns Add0~736 5 COMB LCCOMB_X1_Y32_N10 1 " "Info: 5: + IC(0.259 ns) + CELL(0.420 ns) = 7.638 ns; Loc. = LCCOMB_X1_Y32_N10; Fanout = 1; COMB Node = 'Add0~736'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.679 ns" { Add0~734 Add0~736 } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.275 ns) + CELL(0.438 ns) 8.351 ns Add0~737 6 COMB LCCOMB_X1_Y32_N14 1 " "Info: 6: + IC(0.275 ns) + CELL(0.438 ns) = 8.351 ns; Loc. = LCCOMB_X1_Y32_N14; Fanout = 1; COMB Node = 'Add0~737'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.713 ns" { Add0~736 Add0~737 } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 8.435 ns q_int\[2\] 7 REG LCFF_X1_Y32_N15 1 " "Info: 7: + IC(0.000 ns) + CELL(0.084 ns) = 8.435 ns; Loc. = LCFF_X1_Y32_N15; Fanout = 1; REG Node = 'q_int\[2\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { Add0~737 q_int[2] } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.852 ns ( 33.81 % ) " "Info: Total cell delay = 2.852 ns ( 33.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.583 ns ( 66.19 % ) " "Info: Total interconnect delay = 5.583 ns ( 66.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "8.435 ns" { ld always0~48 Add0~731 Add0~734 Add0~736 Add0~737 q_int[2] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "8.435 ns" { ld ld~combout always0~48 Add0~731 Add0~734 Add0~736 Add0~737 q_int[2] } { 0.000ns 0.000ns 4.782ns 0.267ns 0.000ns 0.259ns 0.275ns 0.000ns } { 0.000ns 0.832ns 0.275ns 0.393ns 0.410ns 0.420ns 0.438ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 10 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.670 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 1 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 4 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 1 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.016 ns) + CELL(0.537 ns) 2.670 ns q_int\[2\] 3 REG LCFF_X1_Y32_N15 1 " "Info: 3: + IC(1.016 ns) + CELL(0.537 ns) = 2.670 ns; Loc. = LCFF_X1_Y32_N15; Fanout = 1; REG Node = 'q_int\[2\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.553 ns" { clk~clkctrl q_int[2] } "NODE_NAME" } } { "UpDnCnt.v" "" { Text "D:/esdp/egs205/Lab4/UpDnCnt/UpDnCnt.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.53 % ) " "Info: Total cell delay = 1.536 ns ( 57.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.134 ns ( 42.47 % ) " "Info: Total interconnect delay = 1.134 ns ( 42.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.670 ns" { clk clk~clkctrl q_int[2] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.670 ns" { clk clk~combout clk~clkctrl q_int[2] } { 0.000ns 0.000ns 0.118ns 1.016ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "8.435 ns" { ld always0~48 Add0~731 Add0~734 Add0~736 Add0~737 q_int[2] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "8.435 ns" { ld ld~combout always0~48 Add0~731 Add0~734 Add0~736 Add0~737 q_int[2] } { 0.000ns 0.000ns 4.782ns 0.267ns 0.000ns 0.259ns 0.275ns 0.000ns } { 0.000ns 0.832ns 0.275ns 0.393ns 0.410ns 0.420ns 0.438ns 0.084ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.670 ns" { clk clk~clkctrl q_int[2] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.670 ns" { clk clk~combout clk~clkctrl q_int[2] } { 0.000ns 0.000ns 0.118ns 1.016ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}