updncnt.map.smsg

universal count un iversal count

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Mon Jan 14 20:23:03 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UpDnCnt -c UpDnCnt
Info: Found 1 design units, including 1 entities, in source file UpDnCnt.v
    Info: Found entity 1: UpDnCnt
Info: Elaborating entity "UpDnCnt" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at UpDnCnt.v(30): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at UpDnCnt.v(35): truncated value with size 32 to match size of target (4)
Info: Duplicate registers merged to single register
    Info: Duplicate register "always0~10" merged to single register "always0~6"
    Info: Duplicate register "always0~19" merged to single register "always0~6"
    Info: Duplicate register "always0~24" merged to single register "always0~6"
Warning: Converting TRI node "always0~29" that feeds logic to an OR gate
Warning: Converting TRI node "always0~25" that feeds logic to an OR gate
Warning: Converting TRI node "always0~20" that feeds logic to an OR gate
Warning: Converting TRI node "always0~11" that feeds logic to an OR gate
Info: Implemented 32 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 8 output pins
    Info: Implemented 14 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Allocated 131 megabytes of memory during processing
    Info: Processing ended: Mon Jan 14 20:23:22 2008
    Info: Elapsed time: 00:00:19