updncnt_tb.v.bak

universal count un iversal count

`timescale 100ms/10ms

module UpDnCnt_tb;
    
reg clk, clr,up, dn, en, ld;
reg [3:0] d; 

wire [3:0] q_int,q ;

UpDnCnt uu1(en,clr,clk,ld,up,dn);

initial
	clk=1'b0;
	always
	#10 clk = ~clk;
	
initial

begin
    
	d=4'b1100;
	en=1'b0;
	ld=1'b0;
	clr=1'b0;
	up=1'b0;
	dn=1'b0;
	#40 en=1'b1;ld=1'b1;up=1'b1;dn=1'b1;
	#40 clr=1'b1;	
	#40 dn=1'b0;	
	#40 up=1'b0;dn=1'b1;
	#40 dn=1'b0;
	#40 ld=1'b0;up=1'b1;
	#40 up=1'b0;	dn=1'b1;
		
	#100 $stop; 			
	
	end
	
endmodule