_primary.vhd

来自「universal count un iversal count」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity UpDnCnt is
    port(
        en              : in     vl_logic;
        clr             : in     vl_logic;
        clk             : in     vl_logic;
        ld              : in     vl_logic;
        up              : in     vl_logic;
        dn              : in     vl_logic;
        d               : in     vl_logic_vector(3 downto 0);
        q               : inout  vl_logic_vector(3 downto 0)
    );
end UpDnCnt;