synth_test.vhd

DAC converter design with Verilog code and testbench

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.free_dac_lib.all;

entity synth_test is
  port (reset	:in std_logic;
  	clk	:in std_logic;
  	period	:in std_logic_vector (11 downto 0);
  	width	:in std_logic_vector (11 downto 0);
  	dout	:out std_logic);
end synth_test;

architecture arch_synth_test of synth_test is
  signal period_t	:std_logic_vector (period'range);
  signal width_t	:std_logic_vector (width'range);
  signal dout_t		:std_logic;
begin
  -- Register the I/O
  process (reset, clk)
  begin
    if reset='1' then
      period_t <= (others=>'0');
      width_t <= (others=>'0');
      dout <= '0';
    elsif clk'event and clk='1' then
      period_t <= period;
      width_t <= width;
      dout <= dout_t;
    end if;
  end process;
  
  U1: dac_pwm2
  	generic map (period'high+1)
  	port map (reset, clk, period_t, width_t, dout_t);

end arch_synth_test;