makefile

DAC converter design with Verilog code and testbench

# 
NCOGEN = ../../nco/ncogen/ncogen.exe
SPECTRUM = ../../spectrum/spectrum.exe
DAC_SOURCE = ../VHDL/dac.vhd
CP = cp
RM = rm
RMFLAGS = -f


all:   ncotest.vhd  dac.vhd

spectrum:  dac_ds.csv dac_pwm.csv dac_nco.csv

dac_ds.csv:  $(SPECTRUM) dac_ds.log
	$(SPECTRUM) dac_ds.log 100000000 8 512 >dac_ds.csv

dac_pwm.csv:  $(SPECTRUM) dac_pwm.log
	$(SPECTRUM) dac_pwm.log 100000000 8 512 >dac_pwm.csv

dac_nco.csv:  $(SPECTRUM) dac_nco.log
	$(SPECTRUM) dac_nco.log 100000000 16 512 >dac_nco.csv


ncotest.vhd:	$(NCOGEN)
	$(NCOGEN) ncotest nco 16 16 sin 1.0 >ncotest.vhd


dac.vhd:	$(DAC_SOURCE)
	$(CP) $(DAC_SOURCE) dac.vhd


clean:
	$(RM) $(RMFLAGS) ncotest.vhd
	$(RM) $(RMFLAGS) dac.vhd
	$(RM) $(RMFLAGS) dac_ds.log
	$(RM) $(RMFLAGS) dac_pwm.log
	$(RM) $(RMFLAGS) dac_ds.csv
	$(RM) $(RMFLAGS) dac_pwm.csv
	$(RM) $(RMFLAGS) *.BAK
	$(RM) $(RMFLAGS) *.bak

#.PHONY: all clean