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一个圣诞彩灯控制芯片的vrilog源代码

I6[0] => Select~11.IN2
I6[1] => Select~10.IN2
I7[0] => Select~13.IN2
I7[1] => Select~12.IN2
I8[0] => Select~7.IN3
I8[1] => Select~6.IN3
I9[0] => Select~9.IN3
I9[1] => Select~8.IN3
I10[0] => Select~11.IN3
I10[1] => Select~10.IN3
I11[0] => Select~13.IN3
I11[1] => Select~12.IN3
I12[0] => Select~7.IN4
I12[1] => Select~6.IN4
I13[0] => Select~9.IN4
I13[1] => Select~8.IN4
I14[0] => Select~11.IN4
I14[1] => Select~10.IN4
I15[0] => Select~13.IN4
I15[1] => Select~12.IN4
I16[0] => Select~7.IN5
I16[1] => Select~6.IN5
I17[0] => Select~9.IN5
I17[1] => Select~8.IN5
I18[0] => Select~11.IN5
I18[1] => Select~10.IN5
I19[0] => Select~13.IN5
I19[1] => Select~12.IN5
I20[0] => Select~7.IN6
I20[1] => Select~6.IN6
I21[0] => Select~9.IN6
I21[1] => Select~8.IN6
I22[0] => Select~11.IN6
I22[1] => Select~10.IN6
I23[0] => Select~13.IN6
I23[1] => Select~12.IN6


|top|model2:u9
l1[0] <= l1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l1[1] <= l1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l2[0] <= l2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l2[1] <= l2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l3[0] <= l3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l3[1] <= l3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l4[0] <= l4[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l4[1] <= l4[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
c <= c~reg0.DB_MAX_OUTPUT_PORT_TYPE
clk => l1[0]~reg0.CLK
clk => l2[1]~reg0.CLK
clk => l2[0]~reg0.CLK
clk => l3[1]~reg0.CLK
clk => l3[0]~reg0.CLK
clk => l4[1]~reg0.CLK
clk => l4[0]~reg0.CLK
clk => i[4].CLK
clk => i[3].CLK
clk => i[2].CLK
clk => i[1].CLK
clk => i[0].CLK
clk => c~reg0.CLK
clk => l1[1]~reg0.CLK
reset => l1[0]~reg0.ACLR
reset => l2[1]~reg0.ACLR
reset => l2[0]~reg0.ACLR
reset => l3[1]~reg0.ACLR
reset => l3[0]~reg0.ACLR
reset => l4[1]~reg0.ACLR
reset => l4[0]~reg0.ACLR
reset => i[4].ACLR
reset => i[3].ACLR
reset => i[2].ACLR
reset => i[1].ACLR
reset => i[0].ACLR
reset => c~reg0.ACLR
reset => l1[1]~reg0.ACLR
en => l1~0.OUTPUTSELECT
en => l2~0.OUTPUTSELECT
en => l3~0.OUTPUTSELECT
en => l4~0.OUTPUTSELECT
en => c~0.OUTPUTSELECT
en => i~5.OUTPUTSELECT
en => i~6.OUTPUTSELECT
en => i~7.OUTPUTSELECT
en => i~8.OUTPUTSELECT
en => i~9.OUTPUTSELECT


|top|model3:u10
l1[0] <= l1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l1[1] <= l1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l2[0] <= l2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l2[1] <= l2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l3[0] <= l3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l3[1] <= l3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l4[0] <= l4[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l4[1] <= l4[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
c <= c~reg0.DB_MAX_OUTPUT_PORT_TYPE
clk => i[3].CLK
clk => i[2].CLK
clk => i[1].CLK
clk => i[0].CLK
clk => l1[1]~reg0.CLK
clk => l1[0]~reg0.CLK
clk => l2[1]~reg0.CLK
clk => l2[0]~reg0.CLK
clk => l3[1]~reg0.CLK
clk => l3[0]~reg0.CLK
clk => l4[1]~reg0.CLK
clk => l4[0]~reg0.CLK
clk => c~reg0.CLK
clk => i[4].CLK
reset => i[3].ACLR
reset => i[2].ACLR
reset => i[1].ACLR
reset => i[0].ACLR
reset => l1[1]~reg0.ACLR
reset => l1[0]~reg0.ACLR
reset => l2[1]~reg0.ACLR
reset => l2[0]~reg0.ACLR
reset => l3[1]~reg0.ACLR
reset => l3[0]~reg0.ACLR
reset => l4[1]~reg0.ACLR
reset => l4[0]~reg0.ACLR
reset => c~reg0.ACLR
reset => i[4].ACLR
en => l1~0.OUTPUTSELECT
en => l2~0.OUTPUTSELECT
en => l3~0.OUTPUTSELECT
en => l4~0.OUTPUTSELECT
en => c~0.OUTPUTSELECT
en => i~5.OUTPUTSELECT
en => i~6.OUTPUTSELECT
en => i~7.OUTPUTSELECT
en => i~8.OUTPUTSELECT
en => i~9.OUTPUTSELECT


|top|model4:u11
l1[0] <= l1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l1[1] <= l1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l2[0] <= l2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l2[1] <= l2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l3[0] <= l3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l3[1] <= l3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l4[0] <= l4[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l4[1] <= l4[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
c <= c~reg0.DB_MAX_OUTPUT_PORT_TYPE
clk => i[4].CLK
clk => i[3].CLK
clk => i[2].CLK
clk => i[1].CLK
clk => i[0].CLK
clk => l1[1]~reg0.CLK
clk => l1[0]~reg0.CLK
clk => l2[1]~reg0.CLK
clk => l2[0]~reg0.CLK
clk => l3[1]~reg0.CLK
clk => l3[0]~reg0.CLK
clk => l4[1]~reg0.CLK
clk => l4[0]~reg0.CLK
clk => c~reg0.CLK
clk => i[5].CLK
reset => i[4].ACLR
reset => i[3].ACLR
reset => i[2].ACLR
reset => i[1].ACLR
reset => i[0].ACLR
reset => l1[1]~reg0.ACLR
reset => l1[0]~reg0.ACLR
reset => l2[1]~reg0.ACLR
reset => l2[0]~reg0.ACLR
reset => l3[1]~reg0.ACLR
reset => l3[0]~reg0.ACLR
reset => l4[1]~reg0.ACLR
reset => l4[0]~reg0.ACLR
reset => c~reg0.ACLR
reset => i[5].ACLR
en => l1~0.OUTPUTSELECT
en => l1~1.OUTPUTSELECT
en => l2~0.OUTPUTSELECT
en => l2~1.OUTPUTSELECT
en => l3~0.OUTPUTSELECT
en => l3~1.OUTPUTSELECT
en => l4~0.OUTPUTSELECT
en => l4~1.OUTPUTSELECT
en => c~0.OUTPUTSELECT
en => i~6.OUTPUTSELECT
en => i~7.OUTPUTSELECT
en => i~8.OUTPUTSELECT
en => i~9.OUTPUTSELECT
en => i~10.OUTPUTSELECT
en => i~11.OUTPUTSELECT


|top|model5:u12
l1[0] <= l1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l1[1] <= l1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l2[0] <= l2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l2[1] <= l2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l3[0] <= l3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l3[1] <= l3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l4[0] <= l4[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l4[1] <= l4[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
c <= c~reg0.DB_MAX_OUTPUT_PORT_TYPE
clk => i[3].CLK
clk => i[2].CLK
clk => i[1].CLK
clk => i[0].CLK
clk => l1[1]~reg0.CLK
clk => l1[0]~reg0.CLK
clk => l2[1]~reg0.CLK
clk => l2[0]~reg0.CLK
clk => l3[1]~reg0.CLK
clk => l3[0]~reg0.CLK
clk => l4[1]~reg0.CLK
clk => l4[0]~reg0.CLK
clk => c~reg0.CLK
clk => i[4].CLK
reset => i[3].ACLR
reset => i[2].ACLR
reset => i[1].ACLR
reset => i[0].ACLR
reset => l1[1]~reg0.ACLR
reset => l1[0]~reg0.ACLR
reset => l2[1]~reg0.ACLR
reset => l2[0]~reg0.ACLR
reset => l3[1]~reg0.ACLR
reset => l3[0]~reg0.ACLR
reset => l4[1]~reg0.ACLR
reset => l4[0]~reg0.ACLR
reset => c~reg0.ACLR
reset => i[4].ACLR
en => l1~0.OUTPUTSELECT
en => l2~0.OUTPUTSELECT
en => l3~0.OUTPUTSELECT
en => l4~0.OUTPUTSELECT
en => c~0.OUTPUTSELECT
en => i~5.OUTPUTSELECT
en => i~6.OUTPUTSELECT
en => i~7.OUTPUTSELECT
en => i~8.OUTPUTSELECT
en => i~9.OUTPUTSELECT


|top|model6:u13
l1[0] <= l1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l1[1] <= l1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l2[0] <= l2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l2[1] <= l2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l3[0] <= l3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l3[1] <= l3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l4[0] <= l4[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l4[1] <= l4[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
c <= c~reg0.DB_MAX_OUTPUT_PORT_TYPE
clk => i[3].CLK
clk => i[2].CLK
clk => i[1].CLK
clk => i[0].CLK
clk => l1[1]~reg0.CLK
clk => l1[0]~reg0.CLK
clk => l2[1]~reg0.CLK
clk => l2[0]~reg0.CLK
clk => l3[1]~reg0.CLK
clk => l3[0]~reg0.CLK
clk => l4[1]~reg0.CLK
clk => l4[0]~reg0.CLK
clk => c~reg0.CLK
clk => i[4].CLK
reset => i[3].ACLR
reset => i[2].ACLR
reset => i[1].ACLR
reset => i[0].ACLR
reset => l1[1]~reg0.ACLR
reset => l1[0]~reg0.ACLR
reset => l2[1]~reg0.ACLR
reset => l2[0]~reg0.ACLR
reset => l3[1]~reg0.ACLR
reset => l3[0]~reg0.ACLR
reset => l4[1]~reg0.ACLR
reset => l4[0]~reg0.ACLR
reset => c~reg0.ACLR
reset => i[4].ACLR
en => l1~0.OUTPUTSELECT
en => l1~1.OUTPUTSELECT
en => c~0.OUTPUTSELECT
en => i~5.OUTPUTSELECT
en => i~6.OUTPUTSELECT
en => i~7.OUTPUTSELECT
en => i~8.OUTPUTSELECT
en => i~9.OUTPUTSELECT


|top|model7:u14
l1[0] <= l1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l1[1] <= l1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l2[0] <= l2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l2[1] <= l2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l3[0] <= l3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l3[1] <= l3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l4[0] <= l4[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l4[1] <= l4[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
c <= c~reg0.DB_MAX_OUTPUT_PORT_TYPE
clk => i[2].CLK
clk => i[1].CLK
clk => i[0].CLK
clk => l1[1]~reg0.CLK
clk => l1[0]~reg0.CLK
clk => l2[1]~reg0.CLK
clk => l2[0]~reg0.CLK
clk => l3[1]~reg0.CLK
clk => l3[0]~reg0.CLK
clk => l4[1]~reg0.CLK
clk => l4[0]~reg0.CLK
clk => c~reg0.CLK
clk => i[3].CLK
reset => i[2].ACLR
reset => i[1].ACLR
reset => i[0].ACLR
reset => l1[1]~reg0.ACLR
reset => l1[0]~reg0.ACLR
reset => l2[1]~reg0.ACLR
reset => l2[0]~reg0.ACLR
reset => l3[1]~reg0.ACLR
reset => l3[0]~reg0.ACLR
reset => l4[1]~reg0.ACLR
reset => l4[0]~reg0.ACLR
reset => c~reg0.ACLR
reset => i[3].ACLR
en => l1~0.OUTPUTSELECT
en => l2~0.OUTPUTSELECT
en => c~0.OUTPUTSELECT
en => i~4.OUTPUTSELECT
en => i~5.OUTPUTSELECT
en => i~6.OUTPUTSELECT
en => i~7.OUTPUTSELECT


|top|model8:u15
l1[0] <= l1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l1[1] <= l1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l2[0] <= l2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l2[1] <= l2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l3[0] <= l3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l3[1] <= l3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l4[0] <= l4[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l4[1] <= l4[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
clk => l1[0]~reg0.CLK
clk => l2[1]~reg0.CLK
clk => l2[0]~reg0.CLK
clk => l3[1]~reg0.CLK
clk => l3[0]~reg0.CLK
clk => l4[1]~reg0.CLK
clk => l4[0]~reg0.CLK
clk => l1[1]~reg0.CLK
reset => l1[0]~reg0.ACLR
reset => l2[1]~reg0.ACLR
reset => l2[0]~reg0.ACLR
reset => l3[1]~reg0.ACLR
reset => l3[0]~reg0.ACLR
reset => l4[1]~reg0.ACLR
reset => l4[0]~reg0.ACLR
reset => l1[1]~reg0.ACLR
en => l1[1]~reg0.DATAIN
en => l1[0]~reg0.DATAIN
en => l2[1]~reg0.DATAIN
en => l2[0]~reg0.DATAIN
en => l3[1]~reg0.DATAIN
en => l3[0]~reg0.DATAIN
en => l4[1]~reg0.DATAIN
en => l4[0]~reg0.DATAIN


|top|qudou:u16
q <= rs:m4.port0
d => d~0.IN1
clk => clk~0.IN3


|top|qudou:u16|d:m0
q <= q~reg0.DB_MAX_OUTPUT_PORT_TYPE
d => q~reg0.DATAIN
clk => q~reg0.CLK


|top|qudou:u16|d:m1
q <= q~reg0.DB_MAX_OUTPUT_PORT_TYPE
d => q~reg0.DATAIN
clk => q~reg0.CLK


|top|qudou:u16|rs:m4
q <= q~reg0.DB_MAX_OUTPUT_PORT_TYPE
r => always0~1.IN0
r => always0~0.IN0
s => always0~0.IN1
s => always0~1.IN1
clk => q~reg0.CLK


|top|TG:u17
l1[0] <= l1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l1[1] <= l1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l2[0] <= l2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l2[1] <= l2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l3[0] <= l3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l3[1] <= l3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l4[0] <= l4[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
l4[1] <= l4[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ein[0] <= ein[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ein[1] <= ein[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ein[2] <= ein[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ein[3] <= ein[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ein[4] <= ein[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ein[5] <= ein[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ein[6] <= ein[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ein[7] <= ein[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reset => ein[6]~reg0.ACLR
reset => ein[5]~reg0.ACLR
reset => ein[4]~reg0.ACLR
reset => ein[3]~reg0.ACLR
reset => ein[2]~reg0.ACLR
reset => ein[1]~reg0.ACLR
reset => ein[0]~reg0.PRESET
reset => l1[1]~reg0.ACLR
reset => l1[0]~reg0.ACLR
reset => l2[1]~reg0.ACLR
reset => l2[0]~reg0.ACLR
reset => l3[1]~reg0.ACLR
reset => l3[0]~reg0.ACLR
reset => l4[1]~reg0.ACLR
reset => l4[0]~reg0.ACLR
reset => flag[2].ACLR
reset => ein[7]~reg0.ACLR
reset => flag[1].ACLR
reset => flag[0].ACLR
reset => flag[3].ACLR
tg => flag[2].CLK
tg => flag[1].CLK
tg => flag[0].CLK
tg => flag[3].CLK
clk => ein[6]~reg0.CLK
clk => ein[5]~reg0.CLK
clk => ein[4]~reg0.CLK
clk => ein[3]~reg0.CLK
clk => ein[2]~reg0.CLK
clk => ein[1]~reg0.CLK
clk => ein[0]~reg0.CLK
clk => l1[1]~reg0.CLK
clk => l1[0]~reg0.CLK
clk => l2[1]~reg0.CLK
clk => l2[0]~reg0.CLK
clk => l3[1]~reg0.CLK
clk => l3[0]~reg0.CLK
clk => l4[1]~reg0.CLK
clk => l4[0]~reg0.CLK
clk => ein[7]~reg0.CLK
I0[0] => Select~9.IN1
I0[1] => Select~8.IN1
I1[0] => Select~11.IN1
I1[1] => Select~10.IN1
I2[0] => Select~13.IN1
I2[1] => Select~12.IN1
I3[0] => Select~15.IN1
I3[1] => Select~14.IN1
I4[0] => Select~9.IN2
I4[1] => Select~8.IN2
I5[0] => Select~11.IN2
I5[1] => Select~10.IN2
I6[0] => Select~13.IN2
I6[1] => Select~12.IN2
I7[0] => Select~15.IN2
I7[1] => Select~14.IN2
I8[0] => Select~9.IN3
I8[1] => Select~8.IN3
I9[0] => Select~11.IN3
I9[1] => Select~10.IN3
I10[0] => Select~13.IN3
I10[1] => Select~12.IN3
I11[0] => Select~15.IN3
I11[1] => Select~14.IN3
I12[0] => Select~9.IN4
I12[1] => Select~8.IN4
I13[0] => Select~11.IN4
I13[1] => Select~10.IN4
I14[0] => Select~13.IN4
I14[1] => Select~12.IN4
I15[0] => Select~15.IN4
I15[1] => Select~14.IN4
I16[0] => Select~9.IN5
I16[1] => Select~8.IN5
I17[0] => Select~11.IN5
I17[1] => Select~10.IN5
I18[0] => Select~13.IN5
I18[1] => Select~12.IN5
I19[0] => Select~15.IN5
I19[1] => Select~14.IN5
I20[0] => Select~9.IN6
I20[1] => Select~8.IN6
I21[0] => Select~11.IN6
I21[1] => Select~10.IN6
I22[0] => Select~13.IN6
I22[1] => Select~12.IN6
I23[0] => Select~15.IN6
I23[1] => Select~14.IN6
I24[0] => Select~9.IN7
I24[1] => Select~8.IN7
I25[0] => Select~11.IN7
I25[1] => Select~10.IN7
I26[0] => Select~13.IN7
I26[1] => Select~12.IN7
I27[0] => Select~15.IN7
I27[1] => Select~14.IN7
I28[0] => Select~9.IN8
I28[1] => Select~8.IN8
I29[0] => Select~11.IN8
I29[1] => Select~10.IN8
I30[0] => Select~13.IN8
I30[1] => Select~12.IN8
I31[0] => Select~15.IN8
I31[1] => Select~14.IN8


|top|huayang:u18
lout <= Select~0.DB_MAX_OUTPUT_PORT_TYPE
clk_bright => Select~0.IN1
clk_medium => Select~0.IN2
clk_dark => Select~0.IN3
lin[0] => Decoder~0.IN1
lin[1] => Decoder~0.IN0


|top|huayang:u19
lout <= Select~0.DB_MAX_OUTPUT_PORT_TYPE
clk_bright => Select~0.IN1
clk_medium => Select~0.IN2
clk_dark => Select~0.IN3
lin[0] => Decoder~0.IN1
lin[1] => Decoder~0.IN0


|top|huayang:u20
lout <= Select~0.DB_MAX_OUTPUT_PORT_TYPE
clk_bright => Select~0.IN1
clk_medium => Select~0.IN2
clk_dark => Select~0.IN3
lin[0] => Decoder~0.IN1
lin[1] => Decoder~0.IN0


|top|huayang:u21
lout <= Select~0.DB_MAX_OUTPUT_PORT_TYPE
clk_bright => Select~0.IN1
clk_medium => Select~0.IN2
clk_dark => Select~0.IN3
lin[0] => Decoder~0.IN1
lin[1] => Decoder~0.IN0