model6_huayang.v

一个圣诞彩灯控制芯片的vrilog源代码

module model6_huayang(l1,l2,l3,l4,clk_bright,clk_medium5,
                      clk_medium4,clk_medium3,clk_medium2,clk_medium1,
                      clk_dark,l11,l22,l33,l44);
input clk_bright,clk_medium5,clk_medium4,
      clk_medium3,clk_medium2,clk_medium1,clk_dark;
input [2:0] l11,l22,l33,l44;
output l1,l2,l3,l4;
wire [2:0] l11,l22,l33,l44;
reg l1,l2,l3,l4;

always /*@(l11 or l22 or l33 or l44) 
begin
  if(l11==1)
    l1=clk_50;
  else
    l1=1'b0;
  if(l22==1)
    l2=clk_50;
  else
    l2=1'b0;
  if(l33==1)
    l3=clk_50;
  else
    l3=1'b0;
  if(l44==1)
    l4=clk_50;
  else
    l4=1'b0;
end */

case({l11,l22,l33,l44})
  12'b000000000000: begin l1=1'b0;       l2=1'b0;       l3=1'b0;       l4=1'b0;    end
  12'b001001001001: begin l1=clk_dark;   l2=clk_dark;   l3=clk_dark;   l4=clk_dark; end
  12'b010010010010: begin l1=clk_medium1;l2=clk_medium1;l3=clk_medium1;l4=clk_medium1; end
  12'b011011011011: begin l1=clk_medium2;l2=clk_medium2;l3=clk_medium2;l4=clk_medium2; end
  12'b100100100100: begin l1=clk_medium3;l2=clk_medium3;l3=clk_medium3;l4=clk_medium3; end
  12'b101101101101: begin l1=clk_medium4;l2=clk_medium4;l3=clk_medium4;l4=clk_medium4; end
  12'b110110110110: begin l1=clk_medium5;l2=clk_medium5;l3=clk_medium5;l4=clk_medium5; end
  12'b111111111111: begin l1=clk_bright; l2=clk_bright; l3=clk_bright; l4=clk_bright;  end
  default:          begin l1=1'b0;      l2=1'b0;      l3=1'b0;      l4=1'b0;   end  
endcase



endmodule