div_4.v

一个圣诞彩灯控制芯片的vrilog源代码

//divid frequency module----2
module div_4(clk4,reset,clk);
parameter number1=16500;
input  clk,reset;
output clk4;
reg    clk4;
reg [14:0] flag;
//initial
    // flag=0;
always @(posedge clk or negedge reset)
if (reset==0)
   flag=15'b000000000000000;
else
 begin 
     if (flag==number1-1)
          begin
            clk4=1'b1;
            flag=15'b000000000000000;
          end
       else
           begin
              flag=flag+15'b000000000000001;
              clk4=1'b0;
            end
end
endmodule