pn_code_1023.v

采用匹配滤波

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    18:47:28 10/28/07
// Design Name:    
// Module Name:    pn_code_1023
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module pn_code_1023(	clk,//时钟
							reset,//复位
							numb,	//0：15
							phase,//0：2
							pn,	//输出伪码
							reg_pn//伪码寄存器输出
							);

	input clk,reset;
	input [3:0]numb;
	input [1:0]phase;
	output pn;
	output [1022:0]reg_pn;

	reg [9:0]numb_1023;
	reg [1022:0]reg_pn;

	reg [9:0]A,B;
	reg pn;
	always @(posedge clk or posedge reset)
		if(reset)
			begin
				pn <= 1'b0;
				numb_1023 <= 10'd1023;
				reg_pn    <= 1023'b0;
				case({numb,phase})
					6'b000000: A <= 10'b1101011010;
					6'b000100: A <= 10'b1101000010;
					6'b001000: A <= 10'b1110110110;
					6'b001100: A <= 10'b1100110010;
					6'b010000: A <= 10'b1100100010;
					6'b010100: A <= 10'b1101100110;
					6'b011000: A <= 10'b1100110110;
					6'b011100: A <= 10'b1101100100;
					6'b100000: A <= 10'b1100110100;
					6'b100100: A <= 10'b1101001010;
					6'b101000: A <= 10'b1111110100;
					6'b101100: A <= 10'b1100101110;
					6'b110000: A <= 10'b1110001000;
					6'b110100: A <= 10'b1100010000;
					6'b111000: A <= 10'b1100111000;
					6'b111100: A <= 10'b1110000000;	
					6'b000001: A <= 10'b1110111001;
					6'b000101: A <= 10'b1100101000;
					6'b001001: A <= 10'b1011010101;
					6'b001101: A <= 10'b0010101111;
					6'b010001: A <= 10'b1011110101;
					6'b010101: A <= 10'b0011111001;
					6'b011001: A <= 10'b1111001010;
					6'b011101: A <= 10'b0010101101;
					6'b100001: A <= 10'b1110011110;
					6'b100101: A <= 10'b0111100011;
					6'b101001: A <= 10'b1111101000;
					6'b101101: A <= 10'b1101011011;
					6'b110001: A <= 10'b0111000001;
					6'b110101: A <= 10'b0001001111;
					6'b111001: A <= 10'b1000110000;
					6'b111101: A <= 10'b1100001010;
					6'b000010: A <= 10'b0011100011;
					6'b000110: A <= 10'b0001101010;
					6'b001010: A <= 10'b0101100011;
					6'b001110: A <= 10'b1110011101;
					6'b010010: A <= 10'b0111010111;
					6'b010110: A <= 10'b1110011111;
					6'b011010: A <= 10'b0011111100;
					6'b011110: A <= 10'b1111001001;
					6'b100010: A <= 10'b0010101010;
					6'b100110: A <= 10'b1010101001;
					6'b101010: A <= 10'b0000011100;
					6'b101110: A <= 10'b0001110101;
					6'b110010: A <= 10'b1001001001;
					6'b110110: A <= 10'b1101011111;
					6'b111010: A <= 10'b0100001000;
					6'b111110: A <= 10'b0010001010;
					default: A <= 10'b0;
				endcase
				case(phase)
					2'b00: B <= 10'b1001_0010_00;	
					2'b01: B <= 10'b0001_1000_01;
					2'b10: B <= 10'b1000_1010_01;
					default : B <= 10'b0; 
				endcase
			end
		else
			begin
				if (numb_1023 > 0)
					begin
						numb_1023 <= numb_1023 - 1'b1;
						reg_pn[numb_1023] <=	A[0] ^ B[0];
					end
				B[9] 		<= B[7] ^ B[0];
				B[8:0] 	<= B[9:1];
				A[9] 		<= A[8] ^ A[7] ^ A[4] ^ A[2] ^ A[1] ^ A[0];
				A[8:0] 	<= A[9:1];
				pn 		<= A[0] ^ B[0];
			end

endmodule