core.tpl

采用匹配滤波

[COREGEN.VERILOG Component Instantiation.div3]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="div3 YourInstanceName ("
text007="    .dividend(dividend),"
text008="    .divisor(divisor),"
text009="    .quot(quot),"
text010="    .remd(remd),"
text011="    .clk(clk),"
text012="    .rfd(rfd),"
text013="    .aclr(aclr),"
text014="    .sclr(sclr),"
text015="    .ce(ce));"
text016=""
text017=" "
type=template
[COREGEN.VERILOG Component Instantiation.encode12_s]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="encode12_s YourInstanceName ("
text007="    .data_in(data_in),"
text008="    .data_out_v(data_out_v),"
text009="    .nd(nd),"
text010="    .rdy(rdy),"
text011="    .aclr(aclr),"
text012="    .clk(clk));"
text013=""
text014=" "
type=template
[COREGEN.VERILOG Component Instantiation.encode34_s]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="encode34_s YourInstanceName ("
text007="    .data_in(data_in),"
text008="    .data_out_s(data_out_s),"
text009="    .nd(nd),"
text010="    .rfd(rfd),"
text011="    .rdy(rdy),"
text012="    .aclr(aclr),"
text013="    .clk(clk));"
text014=""
text015=" "
type=template
[COREGEN.VHDL Component Instantiation.div3]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component div3"
text005="    port ("
text006="    dividend: IN std_logic_VECTOR(30 downto 0);"
text007="    divisor: IN std_logic_VECTOR(2 downto 0);"
text008="    quot: OUT std_logic_VECTOR(30 downto 0);"
text009="    remd: OUT std_logic_VECTOR(2 downto 0);"
text010="    clk: IN std_logic;"
text011="    rfd: OUT std_logic;"
text012="    aclr: IN std_logic;"
text013="    sclr: IN std_logic;"
text014="    ce: IN std_logic);"
text015="end component;"
text016=""
text017=""
text018=""
text019=" "
text020="-------------------------------------------------------------"
text021=" "
text022="-- The following code must appear in the VHDL architecture body."
text023="-- Substitute your own instance name and net names."
text024=" "
text025="your_instance_name : div3"
text026="        port map ("
text027="            dividend => dividend,"
text028="            divisor => divisor,"
text029="            quot => quot,"
text030="            remd => remd,"
text031="            clk => clk,"
text032="            rfd => rfd,"
text033="            aclr => aclr,"
text034="            sclr => sclr,"
text035="            ce => ce);"
text036=" "
type=template
[COREGEN.VHDL Component Instantiation.encode12_s]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component encode12_s"
text005="    port ("
text006="    data_in: IN std_logic;"
text007="    data_out_v: OUT std_logic_VECTOR(1 downto 0);"
text008="    nd: IN std_logic;"
text009="    rdy: OUT std_logic;"
text010="    aclr: IN std_logic;"
text011="    clk: IN std_logic);"
text012="end component;"
text013=""
text014=""
text015=""
text016=" "
text017="-------------------------------------------------------------"
text018=" "
text019="-- The following code must appear in the VHDL architecture body."
text020="-- Substitute your own instance name and net names."
text021=" "
text022="your_instance_name : encode12_s"
text023="        port map ("
text024="            data_in => data_in,"
text025="            data_out_v => data_out_v,"
text026="            nd => nd,"
text027="            rdy => rdy,"
text028="            aclr => aclr,"
text029="            clk => clk);"
text030=" "
type=template
[COREGEN.VHDL Component Instantiation.encode34_s]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component encode34_s"
text005="    port ("
text006="    data_in: IN std_logic;"
text007="    data_out_s: OUT std_logic;"
text008="    nd: IN std_logic;"
text009="    rfd: OUT std_logic;"
text010="    rdy: OUT std_logic;"
text011="    aclr: IN std_logic;"
text012="    clk: IN std_logic);"
text013="end component;"
text014=""
text015=""
text016=""
text017=" "
text018="-------------------------------------------------------------"
text019=" "
text020="-- The following code must appear in the VHDL architecture body."
text021="-- Substitute your own instance name and net names."
text022=" "
text023="your_instance_name : encode34_s"
text024="        port map ("
text025="            data_in => data_in,"
text026="            data_out_s => data_out_s,"
text027="            nd => nd,"
text028="            rfd => rfd,"
text029="            rdy => rdy,"
text030="            aclr => aclr,"
text031="            clk => clk);"
text032=" "
type=template