fbusif.vhd

采用匹配滤波

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-- Company: 
-- Engineer:
--
-- Create Date:    13:49:56 01/19/06
-- Design Name:    
-- Module Name:    fbusif - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fbusif is
port(
    CLK        :in     std_logic;--the same clock as feeded to CPLD
    RST        :in     std_logic;
    FBUS_ADR   :in     std_logic_vector(14 downto 0);
    FBUS_DAT   :inout  std_logic_vector(15 downto 0);
    FBUS_CS    :in     std_logic;
    FBUS_RDE   :in     std_logic;
    FBUS_WRE   :in     std_logic;
    addr_out   :out    std_logic_vector(14 downto 0);
    data_in    :in     std_logic_vector(15 downto 0);
    data_out   :out    std_logic_vector(15 downto 0);
    read_ena   :out    std_logic;
    write_ena  :out    std_logic
    );	  
end fbusif;

architecture Behavioral of fbusif is

signal genwre   :std_logic_vector(1 downto 0);
signal genrde   :std_logic_vector(1 downto 0);

begin

----------------------------------------------
--
--     |  |  |  |  |  |  |  |  |  |  
--     ____                _______
--CS       |______________|
--     _______          __________
--WR/RD       |________|
--     _____________    __________
--WENA              |__| 
--     __________    _____________
--RENA           |__|
--
--DIN  ----<//////////////>-------
--
--DOUT -------------<///>---------
--
----------------------------------------------

p0:process(CLK, RST)
begin
    if RST = '1' then
        genwre <= "00";
    elsif rising_edge(CLK) then 
        genwre(0) <= FBUS_CS or FBUS_WRE;
        genwre(1) <= genwre(0);
		write_ena <= genwre(1) and (not genwre(0));
    end if;
end process p0;

p1:process(CLK, RST)
begin
    if RST = '1' then
        genrde <= "00";
    elsif rising_edge(CLK) then         
        genrde(0) <= FBUS_CS or FBUS_RDE;
        read_ena <= genrde(0) and (not (FBUS_CS or FBUS_RDE));
    end if;
end process p1;

p2:process(CLK, RST)
begin
    if RST = '1' then
        data_out <= (others => '0');
        addr_out <= (others => '0');
    elsif rising_edge(CLK) then         
        data_out <= FBUS_DAT;
        addr_out <= FBUS_ADR;
    end if;
end process p2;

FBUS_DAT <= data_in when (FBUS_RDE='0') and (FBUS_CS = '0') else
            (others=>'Z');

end Behavioral;