encode34_s.vhd

采用匹配滤波

--------------------------------------------------------------------------------
--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
--                                                                            --
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
--     FOR A PARTICULAR PURPOSE.                                              --
--                                                                            --
--     Xilinx products are not intended for use in life support               --
--     appliances, devices, or systems. Use in such applications are          --
--     expressly prohibited.                                                  --
--                                                                            --
--     (c) Copyright 1995-2004 Xilinx, Inc.                                   --
--     All rights reserved.                                                   --
--------------------------------------------------------------------------------
-- You must compile the wrapper file encode34_s.vhd when simulating
-- the core, encode34_s. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY encode34_s IS
	port (
	data_in: IN std_logic;
	data_out_s: OUT std_logic;
	nd: IN std_logic;
	rfd: OUT std_logic;
	rdy: OUT std_logic;
	aclr: IN std_logic;
	clk: IN std_logic);
END encode34_s;

ARCHITECTURE encode34_s_a OF encode34_s IS

component wrapped_encode34_s
	port (
	data_in: IN std_logic;
	data_out_s: OUT std_logic;
	nd: IN std_logic;
	rfd: OUT std_logic;
	rdy: OUT std_logic;
	aclr: IN std_logic;
	clk: IN std_logic);
end component;

-- Configuration specification 
	for all : wrapped_encode34_s use entity XilinxCoreLib.convolution_v4_0(behavioral)
		generic map(
			c_has_rffd => 0,
			c_output_rate => 2,
			c_constraint_length => 7,
			c_dual_channel => 0,
			c_punc_output_rate => 4,
			c_punc_input_rate => 3,
			c_has_rdy => 1,
			c_has_sclr => 0,
			c_has_nd => 1,
			c_punc_code1 => 3,
			c_enable_rlocs => 1,
			c_punc_code0 => 5,
			c_has_rfd => 1,
			c_has_ce => 0,
			c_punctured => 1,
			c_has_aclr => 1,
			c_has_fd => 0,
			c_convolution_code6 => 3,
			c_convolution_code5 => 3,
			c_convolution_code4 => 3,
			c_convolution_code3 => 3,
			c_convolution_code2 => 3,
			c_convolution_code1 => 91,
			c_convolution_code0 => 121);
BEGIN

U0 : wrapped_encode34_s
		port map (
			data_in => data_in,
			data_out_s => data_out_s,
			nd => nd,
			rfd => rfd,
			rdy => rdy,
			aclr => aclr,
			clk => clk);
END encode34_s_a;

-- synopsys translate_on