pn_test.tbw

采用匹配滤波

version 3
f:\bpsk_conv_encode\pn_catch_83_test.v
pn_catch_83_test
VERILOG
VHDL
pn_test.xwv
Clocked
-
-
1000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk_110
100000000
100000000
15000000
15000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
reset
clk_110
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clk_110
reset
SIGNAL_ORDER_END
-X-X-X-