pn_catch_83_test.v

采用匹配滤波

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    08:27:24 12/29/07
// Design Name:    
// Module Name:    pn_catch_83_test
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module pn_catch_83_test(clk_110,reset);
	
	input clk_110,reset;

	parameter K_clk7m = 32'd273940823;
	gen_clk 	gc(						//用于生成7.5M时钟
				.clk_110(clk_110),	//
				.reset(reset),			//
				.K(K_clk7m),			//
				.clk(clk_7m));				//

	reg clk_3p5m;
	always @(posedge clk_7m or posedge reset)
		begin
			if (reset)
				clk_3p5m <= 1'b0;
			else
				clk_3p5m <= clk_3p5m + 1'b1;
		end

	wire [1022:0]reg_pn;
	pn_code_1023 pc0_1(	
				.clk(clk_3p5m),
				.reset(reset),
				.numb(4'b0000),
				.phase(2'b00),
				.pn(input_pn),
				.reg_pn(reg_pn));

	wire input_hp_i,input_hp_q;
	assign input_hp_i = input_pn;
	assign input_hp_q = 0;
	
	reg [2045:0]input_i,input_q;

	parameter noise_parameter = 7'd60;
	noise_gen_one_bit ng(clk_7m,reset,noise_parameter,error);

	always @(posedge clk_7m or posedge reset)
		begin
			if (reset)
				begin
					input_i <= 2046'b0;
					input_q <= 2046'b0;
				end
			else
				begin
					input_i <= {input_i[2044:0],input_hp_i ^ error};
					input_q <= {input_q[2044:0],input_hp_q};
				end
		end

	pn_catch pc(clk_7m,reset,input_i,input_q,reg_pn);

endmodule