p2.tbw

采用匹配滤波

version 3
e:\coding_test223\fpgab_top.v
fpgab_top
VERILOG
VERILOG
p2.xwv
Clocked
-
-
100000000
ps
GSR:false
PRLD:false
100000
CLOCK_LIST_BEGIN
clk
4546000
4546000
15000
15000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
ADA_D
clk
AUX_CLK
clk
CLK_ADA
clk
CTRL_BUS
clk
CTRL_CLK
clk
DA1_D
clk
DA2_D
clk
DAC_SCLK
clk
DAC_SDENB
clk
DAC_SDIO
clk
DAC_SDO
clk
DAV1_B
clk
DAV2_B
clk
DA_PLLLOCK
clk
F2F
clk
F2_422_RX
clk
F2_422_TX
clk
F2_BEEP
clk
F2_LED
clk
F2_SW
clk
F2_TTL_RX
clk
F2_TTL_TX
clk
IRQ_EN
clk
IRQ_F2
clk
RST_DAC
clk
TEST_D
clk
clk10
clk
clk_out
clk
reset_in
clk
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
ADA_D_DIFF
CLK_ADA_DIFF
DA1_D_DIFF
DA2_D_DIFF
DAC_SCLK_DIFF
DAC_SDENB_DIFF
DAV1_B_DIFF
DAV2_B_DIFF
F2_422_TX_DIFF
F2_BEEP_DIFF
F2_LED_DIFF
F2_TTL_TX_DIFF
IRQ_F2_DIFF
RST_DAC_DIFF
TEST_D_DIFF
clk_out_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clk
CTRL_CLK
DAC_SDO
DA_PLLLOCK
IRQ_EN
clk10
reset_in
AUX_CLK
F2_422_RX
F2_SW
F2_TTL_RX
CLK_ADA
DAC_SCLK
DAC_SDENB
F2_BEEP
IRQ_F2
RST_DAC
clk_out
ADA_D
DA1_D
DA2_D
DAV1_B
DAV2_B
F2_422_TX
F2_LED
F2_TTL_TX
TEST_D
DAC_SDIO
CTRL_BUS
F2F
SIGNAL_ORDER_END
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