viterbi.vhd

采用匹配滤波

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-- You must compile the wrapper file viterbi.vhd when simulating
-- the core, viterbi. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY viterbi IS
	port (
	data_in0: IN std_logic_VECTOR(2 downto 0);
	data_out: OUT std_logic;
	rdy: OUT std_logic;
	aclr: IN std_logic;
	clk: IN std_logic);
END viterbi;

ARCHITECTURE viterbi_a OF viterbi IS

component wrapped_viterbi
	port (
	data_in0: IN std_logic_VECTOR(2 downto 0);
	data_out: OUT std_logic;
	rdy: OUT std_logic;
	aclr: IN std_logic;
	clk: IN std_logic);
end component;

-- Configuration specification 
	for all : wrapped_viterbi use entity XilinxCoreLib.viterbi_v3_0(behavioral)
		generic map(
			c_best_state_bwr => 0,
			c_has_sync => 0,
			c_constraint_length => 7,
			c_has_sclr => 0,
			c_red_latency => 0,
			c_convolution0_code6 => 0,
			c_traceback_length => 66,
			c_convolution0_code5 => 0,
			c_convolution1_code6 => 0,
			c_convolution0_code4 => 0,
			c_convolution1_code5 => 0,
			c_convolution0_code3 => 0,
			c_convolution1_code4 => 0,
			c_convolution0_code2 => 0,
			c_convolution1_code3 => 0,
			c_convolution0_code1 => 91,
			c_convolution1_code2 => 0,
			c_convolution0_code0 => 121,
			c_convolution1_code1 => 91,
			c_convolution1_code0 => 121,
			c_has_best_state => 0,
			c_punc_code1 => 3,
			c_soft_coding => 1,
			c_punc_code0 => 5,
			c_punctured => 1,
			c_soft_width => 3,
			c_trellis_mode => 0,
			c_channel_count => 1,
			c_punc_input_rate => 3,
			c_has_rdy => 1,
			c_max_rate => 2,
			c_has_erased => 0,
			c_has_rffd => 0,
			c_ber_rate => 20,
			c_dual_decoder => 0,
			c_radix4 => 0,
			c_serial => 0,
			c_has_sync_thresh => 0,
			snr => 20,
			c_output_rate1 => 2,
			c_has_aclr => 1,
			c_output_rate0 => 2,
			bit_limit => 100,
			c_has_norm => 0,
			c_has_block_valid => 0,
			c_compare => 0,
			c_soft_code => 0,
			c_has_ce => 0,
			c_has_ber => 0,
			c_convcode1_radix => 2,
			c_convcode0_radix => 2,
			c_has_fd => 0);
BEGIN

U0 : wrapped_viterbi
		port map (
			data_in0 => data_in0,
			data_out => data_out,
			rdy => rdy,
			aclr => aclr,
			clk => clk);
END viterbi_a;

-- synopsys translate_on