_primary.vhd

来自「采用匹配滤波」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity clk_loop_4 is
    port(
        clk             : in     vl_logic;
        clk_main        : in     vl_logic;
        dclkm4          : out    vl_logic;
        reset           : in     vl_logic;
        add_cy_31_bit   : in     vl_logic_vector(30 downto 0)
    );
end clk_loop_4;