_primary.vhd

来自「采用匹配滤波」· VHDL 代码 · 共 42 行

library verilog;
use verilog.vl_types.all;
entity fpgab_top is
    generic(
        Uncode          : integer := 0;
        Code12          : integer := 1;
        Code34          : integer := 2
    );
    port(
        clk             : in     vl_logic;
        clk10           : in     vl_logic;
        clk_out         : out    vl_logic;
        reset_in        : in     vl_logic;
        DA1_D           : out    vl_logic_vector(15 downto 0);
        DA2_D           : out    vl_logic_vector(15 downto 0);
        RST_DAC         : out    vl_logic;
        DAC_SCLK        : out    vl_logic;
        DAC_SDENB       : out    vl_logic;
        DAC_SDIO        : inout  vl_logic;
        DAC_SDO         : in     vl_logic;
        DA_PLLLOCK      : in     vl_logic;
        DAV1_B          : out    vl_logic_vector(5 downto 0);
        DAV2_B          : out    vl_logic_vector(5 downto 0);
        ADA_D           : out    vl_logic_vector(7 downto 0);
        CLK_ADA         : out    vl_logic;
        AUX_CLK         : in     vl_logic_vector(2 downto 0);
        CTRL_CLK        : in     vl_logic;
        CTRL_BUS        : inout  vl_logic_vector(35 downto 0);
        IRQ_EN          : in     vl_logic;
        IRQ_F2          : out    vl_logic;
        F2_422_RX       : in     vl_logic_vector(7 downto 0);
        F2_422_TX       : out    vl_logic_vector(7 downto 0);
        F2_TTL_RX       : in     vl_logic_vector(3 downto 0);
        F2_TTL_TX       : out    vl_logic_vector(3 downto 0);
        F2F             : inout  vl_logic_vector(89 downto 0);
        F2_BEEP         : out    vl_logic;
        F2_LED          : out    vl_logic_vector(5 downto 0);
        F2_SW           : in     vl_logic_vector(3 downto 0);
        TEST_D          : out    vl_logic_vector(7 downto 0)
    );
end fpgab_top;