_primary.vhd

来自「采用匹配滤波」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity bit_stat is
    port(
        bit_clk         : in     vl_logic;
        bit_data        : in     vl_logic_vector(2 downto 0);
        reset           : in     vl_logic;
        stat00          : out    vl_logic_vector(15 downto 0);
        stat01          : out    vl_logic_vector(15 downto 0);
        stat10          : out    vl_logic_vector(15 downto 0);
        stat11          : out    vl_logic_vector(15 downto 0)
    );
end bit_stat;