_primary.vhd

来自「采用匹配滤波」· VHDL 代码 · 共 22 行

library verilog;
use verilog.vl_types.all;
entity encode_BPSK is
    generic(
        Uncode          : integer := 0;
        Code12          : integer := 1;
        Code34          : integer := 2
    );
    port(
        data_clk        : in     vl_logic;
        datain          : in     vl_logic;
        reset           : in     vl_logic;
        clk110          : in     vl_logic;
        code_clk        : out    vl_logic;
        code_out        : out    vl_logic;
        code_rate       : in     vl_logic_vector(1 downto 0);
        add_cy_31_bit   : in     vl_logic_vector(30 downto 0);
        qufan           : in     vl_logic;
        overflow        : out    vl_logic
    );
end encode_BPSK;