_primary.vhd

来自「采用匹配滤波」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity encode34_s is
    port(
        data_in         : in     vl_logic;
        data_out_s      : out    vl_logic;
        nd              : in     vl_logic;
        rfd             : out    vl_logic;
        rdy             : out    vl_logic;
        aclr            : in     vl_logic;
        clk             : in     vl_logic
    );
end encode34_s;