_primary.vhd

来自「采用匹配滤波」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity frame_syn_judge is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        data0_vtb       : in     vl_logic;
        syn_zhi         : out    vl_logic
    );
end frame_syn_judge;