_primary.vhd

来自「采用匹配滤波」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity dcm165m is
    port(
        CLKIN_IN        : in     vl_logic;
        RST_IN          : in     vl_logic;
        CLKFX_OUT       : out    vl_logic;
        CLK0_OUT        : out    vl_logic;
        LOCKED_OUT      : out    vl_logic
    );
end dcm165m;