_primary.vhd

来自「采用匹配滤波」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity multi_clk_gen is
    port(
        clk110          : in     vl_logic;
        up150k          : in     vl_logic;
        clk_main        : out    vl_logic;
        reset           : in     vl_logic
    );
end multi_clk_gen;