_primary.vhd

采用匹配滤波

library verilog;
use verilog.vl_types.all;
entity clk_en_numb is
    port(
        dclkm4          : in     vl_logic;
        reset           : in     vl_logic;
        en_numb_double  : out    vl_logic_vector(4 downto 0)
    );
end clk_en_numb;