prev_cmp_pngenchuan_18.map.qmsg

生成18级的m序列的VerilogHDL程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 23 15:08:36 2008 " "Info: Processing started: Wed Jan 23 15:08:36 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PNGENchuan_18 -c PNGENchuan_18 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PNGENchuan_18 -c PNGENchuan_18" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "PNGENchuan_18.v 1 1 " "Warning: Using design file PNGENchuan_18.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 PNGENchuan_18 " "Info: Found entity 1: PNGENchuan_18" {  } { { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "PNGENchuan_18 " "Info: Elaborating entity \"PNGENchuan_18\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } } { "PNGENchuan_18.v" "" { Text "E:/DataLinkProject/Model/PN_chuan/PNGENchuan_18.v" 25 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "23 " "Info: Implemented 23 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "19 " "Info: Implemented 19 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Allocated 145 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 23 15:08:43 2008 " "Info: Processing ended: Wed Jan 23 15:08:43 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}