__projnav.log

用Verilog实现的串口异步通信

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\found.000\uart/_ngo -nt timestamp
-uc uart_constraints.ucf -p xc4vsx35-ff668-10 uart.ngc uart.ngd 

Reading NGO file 'D:/FOUND.000/uart/uart.ngc' ...
Reading module "ila.ngo" ( "ila.ngo" unchanged since last run )...
Loading design module "d:\found.000\uart\_ngo\ila.ngo"...
Reading module "icon.ngo" ( "icon.ngo" unchanged since last run )...
Loading design module "d:\found.000\uart\_ngo\icon.ngo"...

Applying constraints in "uart_constraints.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "uart.ngd" ...

Writing NGDBUILD log file "uart.bld"...

NGDBUILD done.




Started process "Map".

Using target part "4vsx35ff668-10".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:         424 out of  30,720    1%
  Number of 4 input LUTs:             335 out of  30,720    1%
Logic Distribution:
  Number of occupied Slices:                          451 out of  15,360    2%
    Number of Slices containing only related logic:     451 out of     451  100%
    Number of Slices containing unrelated logic:          0 out of     451    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            523 out of  30,720    1%
  Number used as logic:                335
  Number used as a route-thru:          87
  Number used as Shift registers:      101
  Number of bonded IOBs:               11 out of     448    2%
  Number of BUFG/BUFGCTRLs:             2 out of      32    6%
    Number used as BUFGs:                2
    Number used as BUFGCTRLs:            0
  Number of FIFO16/RAMB16s:             9 out of     192    4%
    Number used as FIFO16s:              0
    Number used as RAMB16s:              9
  Number of BSCAN_VIRTEX4s:             1 out of       4   25%

   Number of RPM macros:           12
Total equivalent gate count for design:  13,113
Additional JTAG gate count for IOBs:  528
Peak Memory Usage:  204 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "uart_map.mrp" for details.




Started process "Place & Route".




Constraints file: uart.pcf.
Loading device for application Rf_Device from file '4vsx35.nph' in environment
C:/Xilinx.
   "uart" is an NCD, version 3.1, device xc4vsx35, package ff668, speed -10
This design is using the default stepping level (major silicon revision) for
this device (1). Unless your design is targeted at devices of this stepping
level, it is recommended that you explicitly specify the stepping level of the
parts you will be using. This will allow the tools to take advantage of any
available performance and functional enhancements for this device. The latest
stepping level for this device is '2'. Additional information on "stepping
level" is available at support.xilinx.com.

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.200 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:2666 - Constraint ignored: PATH "TS_U_TO_D_path" TIG;

Device speed data version:  "PRODUCTION 1.57 2005-08-24".


Device Utilization Summary:

   Number of BSCANs                    1 out of 4      25%
   Number of BUFGs                     2 out of 32      6%
   Number of ILOGICs                   1 out of 448     1%
   Number of External IOBs            11 out of 448     2%
      Number of LOCed IOBs             3 out of 11     27%

   Number of RAMB16s                   9 out of 192     4%
   Number of Slices                  451 out of 15360   2%
      Number of SLICEMs               65 out of 7680    1%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 7 secs 
Finished initial Timing Analysis.  REAL time: 7 secs 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98c1cf) REAL time: 8 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 8 secs 

Phase 3.2
.....
WARNING:Place:644 - A clock IOB  clock component is not placed at an optimal
   clock IOB site  The clock IOB component <CLK> is placed at site IOB_X1Y58.
   The clock IO site can use the fast path between the IO and the Clock
   buffer/GCLK if the IOB is placed in the master Clock IOB Site. This is
   normally an ERROR but the environment variable
   XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING is set allowing your design to continue.


Phase 3.2 (Checksum:989c5b) REAL time: 46 secs 

Phase 4.30
Phase 4.30 (Checksum:26259fc) REAL time: 46 secs 

Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 46 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 46 secs 

Phase 7.8
.........................................................
........
Phase 7.8 (Checksum:a841d3) REAL time: 47 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 47 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 47 secs 

Phase 10.27
Phase 10.27 (Checksum:5f5e0f6) REAL time: 48 secs 

Phase 11.5
Phase 11.5 (Checksum:68e7775) REAL time: 48 secs 

Writing design to file uart.ncd


Total REAL time to Placer completion: 48 secs 
Total CPU time to Placer completion: 48 secs 

Starting Router

Phase 1: 3160 unrouted;       REAL time: 50 secs 

Phase 2: 2506 unrouted;       REAL time: 1 mins 4 secs 

Phase 3: 657 unrouted;       REAL time: 1 mins 4 secs 

Phase 4: 657 unrouted; (0)      REAL time: 1 mins 4 secs 

Phase 5: 657 unrouted; (0)      REAL time: 1 mins 4 secs 

Phase 6: 657 unrouted; (0)      REAL time: 1 mins 4 secs 

Phase 7: 0 unrouted; (0)      REAL time: 1 mins 5 secs 

Phase 8: 0 unrouted; (0)      REAL time: 1 mins 6 secs 

Phase 9: 0 unrouted; (0)      REAL time: 1 mins 6 secs 

Total REAL time to Router completion: 1 mins 7 secs 
Total CPU time to Router completion: 1 mins 6 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|         control0<0> | BUFGCTRL_X0Y0| No   |   92 |  0.246     |  2.891      |
+---------------------+--------------+------+------+------------+-------------+
|           CLK_BUFGP | BUFGCTRL_X0Y1| No   |  218 |  0.382     |  2.902      |
+---------------------+--------------+------+------+------------+-------------+
|  i_icon/iupdate_out |         Local|      |    1 |  0.000     |  0.985      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_J_TO_J = MAXDELAY FROM TIMEGRP "J_CLK" | 30.000ns   | 7.117ns    | 6    
   TO TIMEGRP "J_CLK" 30 ns                 |            |            |      
--------------------------------------------------------------------------------
  TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" | 15.000ns   | 2.426ns    | 1    
   TO TIMEGRP "J_CLK" 15 ns                 |            |            |      
--------------------------------------------------------------------------------
  TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" | 15.000ns   | 0.968ns    | 0    
   TO TIMEGRP "U_CLK" 15 ns                 |            |            |      
--------------------------------------------------------------------------------
  PATH "TS_U_TO_D_path" TIG                 | N/A        | N/A        | N/A  
--------------------------------------------------------------------------------
  PATH "TS_J_TO_D_path" TIG                 | N/A        | 4.991ns    | 1    
--------------------------------------------------------------------------------
  PATH "TS_D_TO_J_path" TIG                 | N/A        | 4.871ns    | 5    
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 1 mins 9 secs 
Total CPU time to PAR completion: 1 mins 8 secs 

Peak Memory Usage:  200 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 2
Number of info messages: 0

Writing design to file uart.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '4vsx35.nph' in environment
C:/Xilinx.
   "uart" is an NCD, version 3.1, device xc4vsx35, package ff668, speed -10
This design is using the default stepping level (major silicon revision) for
this device (1). Unless your design is targeted at devices of this stepping
level, it is recommended that you explicitly specify the stepping level of the
parts you will be using. This will allow the tools to take advantage of any
available performance and functional enhancements for this device. The latest
stepping level for this device is '2'. Additional information on "stepping
level" is available at support.xilinx.com.
WARNING:Timing:2666 - Constraint ignored: PATH "TS_U_TO_D_path" TIG;

Analysis completed Sat Jan 12 16:40:27 2008
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 1
Total time: 7 secs 







Started process "Generate Programming File".