__projnav.log

用Verilog实现的串口异步通信

Synthesizing Unit <uart>.
    Related source file is "uart.v".
    Found 8-bit register for signal <data1>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0001>.
    Found 1-bit register for signal <busy>.
    Found 30-bit up counter for signal <cnt1>.
    Found 26-bit up counter for signal <cnt2>.
    Found 1-bit register for signal <flag>.
    Found 1-bit register for signal <hunt>.
    Found 1-bit register for signal <hunt1>.
    Found 10-bit register for signal <rxdata>.
    Summary:
	inferred   2 Counter(s).
	inferred  22 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <uart> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
MAC inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
DSP optimizations ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 5
 26-bit up counter                 : 2
 30-bit up counter                 : 2
 4-bit up counter                  : 1
# Registers                        : 18
 1-bit register                    : 17
 8-bit register                    : 1
# Multiplexers                     : 1
 1-bit 4-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Executing edif2ngd -noa "ila.edn" "ila.ngo"
Release 7.1.04i - edif2ngd H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
INFO:NgdBuild - Release 7.1.04i edif2ngd H.42
INFO:NgdBuild - Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Applying constraints in "ila.ncf" to module "ila"...
Writing module to "ila.ngo"...
Executing edif2ngd -noa "icon.edn" "icon.ngo"
Release 7.1.04i - edif2ngd H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
INFO:NgdBuild - Release 7.1.04i edif2ngd H.42
INFO:NgdBuild - Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Applying constraints in "icon.ncf" to module "icon"...
Writing module to "icon.ngo"...
WARNING:Xst:1474 - Core <ila> was not loaded for <i_ila> as one or more ports did not line up with component declaration.  Declared input port <control<35>> was not found in the core.  Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions.
WARNING:Xst:1474 - Core <icon> was not loaded for <i_icon> as one or more ports did not line up with component declaration.  Declared output port <control0<3>> was not found in the core.  Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions.
WARNING:Xst:1291 - FF/Latch <data_out_flag> is unconnected in block <u1>.

Optimizing unit <uart> ...

Optimizing unit <send> ...
Loading device for application Rf_Device from file '4vsx35.nph' in environment C:/Xilinx.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <u1/data_out_flag> is unconnected in block <uart>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block uart, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 4vsx35ff668-10 

 Number of Slices:                     165  out of  15360     1%  
 Number of Slice Flip Flops:           140  out of  30720     0%  
 Number of 4 input LUTs:               301  out of  30720     0%  
 Number of bonded IOBs:                 11  out of    450     2%  
 Number of GCLKs:                        1  out of     32     3%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 140   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -10

   Minimum period: 5.464ns (Maximum Frequency: 182.999MHz)
   Minimum input arrival time before clock: 3.689ns
   Maximum output required time after clock: 4.869ns
   Maximum combinational path delay: 1.643ns

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\found.000\uart/_ngo -nt timestamp
-uc uart_constraints.ucf -p xc4vsx35-ff668-10 uart.ngc uart.ngd 

Reading NGO file 'D:/FOUND.000/uart/uart.ngc' ...
Executing edif2ngd -noa "ila.edn" "d:\found.000\uart\_ngo\ila.ngo"
Release 7.1.04i - edif2ngd H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
INFO:NgdBuild - Release 7.1.04i edif2ngd H.42
INFO:NgdBuild - Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Applying constraints in "ila.ncf" to module "ila"...
Writing module to "d:/found.000/uart/_ngo/ila.ngo"...
Loading design module "d:\found.000\uart\_ngo\ila.ngo"...
Executing edif2ngd -noa "icon.edn" "d:\found.000\uart\_ngo\icon.ngo"
Release 7.1.04i - edif2ngd H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
INFO:NgdBuild - Release 7.1.04i edif2ngd H.42
INFO:NgdBuild - Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Applying constraints in "icon.ncf" to module "icon"...
Writing module to "d:/found.000/uart/_ngo/icon.ngo"...
Loading design module "d:\found.000\uart\_ngo\icon.ngo"...

Applying constraints in "uart_constraints.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "uart.ngd" ...

Writing NGDBUILD log file "uart.bld"...

NGDBUILD done.


Project Navigator Auto-Make Log File
-------------------------------------







Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "send.v"
Module <send> compiled
Compiling verilog file "icon_xst_example.v"
Module <icon_xst_example> compiled
Module <icon> compiled
Compiling verilog file "ila_xst_example.v"
Module <ila_xst_example> compiled
Module <ila> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
No errors in compilation
Analysis of file <"uart.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <uart>.
Module <uart> is correct for synthesis.
 
Analyzing module <send>.
Module <send> is correct for synthesis.
 
Analyzing module <icon>.
Generating a Black Box for module <icon>.
 
Analyzing module <ila>.
Generating a Black Box for module <ila>.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <send>.
    Related source file is "send.v".
    Found 1-bit register for signal <data_out>.
    Found 1-bit register for signal <data_out_flag>.
    Found 1-bit register for signal <busy>.
    Found 4-bit up counter for signal <cnt>.
    Found 30-bit up counter for signal <cnt1>.
    Found 26-bit up counter for signal <cnt2>.
    Summary:
	inferred   3 Counter(s).
	inferred   3 D-type flip-flop(s).
Unit <send> synthesized.


Synthesizing Unit <uart>.
    Related source file is "uart.v".
    Found 8-bit register for signal <data1>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0001>.
    Found 1-bit register for signal <busy>.
    Found 30-bit up counter for signal <cnt1>.
    Found 26-bit up counter for signal <cnt2>.
    Found 1-bit register for signal <flag>.
    Found 1-bit register for signal <hunt>.
    Found 1-bit register for signal <hunt1>.
    Found 10-bit register for signal <rxdata>.
    Summary:
	inferred   2 Counter(s).
	inferred  22 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <uart> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
MAC inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
DSP optimizations ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 5
 26-bit up counter                 : 2
 30-bit up counter                 : 2
 4-bit up counter                  : 1
# Registers                        : 18
 1-bit register                    : 17
 8-bit register                    : 1
# Multiplexers                     : 1
 1-bit 4-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Reading module "ila.ngo" ( "ila.ngo" unchanged since last run )...
Reading module "icon.ngo" ( "icon.ngo" unchanged since last run )...
WARNING:Xst:1474 - Core <ila> was not loaded for <i_ila> as one or more ports did not line up with component declaration.  Declared input port <control<35>> was not found in the core.  Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions.
WARNING:Xst:1474 - Core <icon> was not loaded for <i_icon> as one or more ports did not line up with component declaration.  Declared output port <control0<3>> was not found in the core.  Please make sure that component declaration ports are consistent with the core ports including direction and bus-naming conventions.
WARNING:Xst:1291 - FF/Latch <data_out_flag> is unconnected in block <u1>.

Optimizing unit <uart> ...

Optimizing unit <send> ...
Loading device for application Rf_Device from file '4vsx35.nph' in environment C:/Xilinx.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <u1/data_out_flag> is unconnected in block <uart>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block uart, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 4vsx35ff668-10 

 Number of Slices:                     165  out of  15360     1%  
 Number of Slice Flip Flops:           140  out of  30720     0%  
 Number of 4 input LUTs:               301  out of  30720     0%  
 Number of bonded IOBs:                 11  out of    450     2%  
 Number of GCLKs:                        1  out of     32     3%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 140   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -10

   Minimum period: 5.464ns (Maximum Frequency: 182.999MHz)
   Minimum input arrival time before clock: 3.689ns
   Maximum output required time after clock: 4.869ns
   Maximum combinational path delay: 1.643ns