__projnav.log

用Verilog实现的串口异步通信

Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "send.v"
ERROR:HDLCompilers:26 - "send.v" line 25 expecting ';', found '='
ERROR:HDLCompilers:28 - "send.v" line 49 'cnnt2' has not been declared
ERROR:HDLCompilers:26 - "send.v" line 66 expecting ':', found ';'
ERROR:HDLCompilers:28 - "send.v" line 66 'b0001' has not been declared
ERROR:HDLCompilers:28 - "send.v" line 79 'data_out_fkag' has not been declared
Module <send> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Analysis of file <"uart.prj"> failed.
--> 

Total memory usage is 77224 kilobytes

Number of errors   :    5 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "send.v"
Module <send> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
ERROR:HDLCompilers:247 - "send.v" line 56 Reference to scalar wire 'data_out_flag' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "send.v" line 56 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "send.v" line 65 Reference to scalar wire 'data_out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "send.v" line 65 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "send.v" line 66 Reference to scalar wire 'data_out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "send.v" line 66 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "send.v" line 67 Reference to scalar wire 'data_out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "send.v" line 67 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "send.v" line 68 Reference to scalar wire 'data_out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "send.v" line 68 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "send.v" line 69 Reference to scalar wire 'data_out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "send.v" line 69 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "send.v" line 70 Reference to scalar wire 'data_out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "send.v" line 70 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "send.v" line 71 Reference to scalar wire 'data_out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "send.v" line 71 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "send.v" line 72 Reference to scalar wire 'data_out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "send.v" line 72 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "send.v" line 73 Reference to scalar wire 'data_out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "send.v" line 73 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "send.v" line 74 Reference to scalar wire 'data_out' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "send.v" line 74 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "send.v" line 79 Reference to scalar wire 'data_out_flag' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "send.v" line 79 Illegal left hand side of nonblocking assignment
ERROR:HDLCompilers:247 - "uart.v" line 49 Reference to vector wire 'data' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "uart.v" line 49 Illegal left hand side of nonblocking assignment
Analysis of file <"uart.prj"> failed.
--> 

Total memory usage is 77224 kilobytes

Number of errors   :   26 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "send.v"
Module <send> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
No errors in compilation
Analysis of file <"uart.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <uart>.
Module <uart> is correct for synthesis.
 
Analyzing module <send>.
Module <send> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <send>.
    Related source file is "send.v".
    Found 1-bit register for signal <data_out>.
    Found 1-bit register for signal <data_out_flag>.
    Found 1-bit register for signal <busy>.
    Found 4-bit up counter for signal <cnt>.
    Found 30-bit up counter for signal <cnt1>.
    Found 26-bit up counter for signal <cnt2>.
    Summary:
	inferred   3 Counter(s).
	inferred   3 D-type flip-flop(s).
Unit <send> synthesized.


Synthesizing Unit <uart>.
    Related source file is "uart.v".
    Found 8-bit register for signal <data>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0001>.
    Found 1-bit register for signal <busy>.
    Found 30-bit up counter for signal <cnt1>.
    Found 26-bit up counter for signal <cnt2>.
    Found 1-bit register for signal <flag>.
    Found 1-bit register for signal <hunt>.
    Found 1-bit register for signal <hunt1>.
    Found 10-bit register for signal <rxdata>.
    Summary:
	inferred   2 Counter(s).
	inferred  22 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <uart> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
MAC inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
DSP optimizations ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 5
 26-bit up counter                 : 2
 30-bit up counter                 : 2
 4-bit up counter                  : 1
# Registers                        : 18
 1-bit register                    : 17
 8-bit register                    : 1
# Multiplexers                     : 1
 1-bit 4-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <data_out_flag> is unconnected in block <u1>.

Optimizing unit <uart> ...

Optimizing unit <send> ...
Loading device for application Rf_Device from file '4vsx35.nph' in environment C:/Xilinx.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <u1/data_out_flag> is unconnected in block <uart>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block uart, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 4vsx35ff668-10 

 Number of Slices:                     168  out of  15360     1%  
 Number of Slice Flip Flops:           140  out of  30720     0%  
 Number of 4 input LUTs:               310  out of  30720     1%  
 Number of bonded IOBs:                 11  out of    450     2%  
 Number of GCLKs:                        1  out of     32     3%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 140   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -10

   Minimum period: 4.977ns (Maximum Frequency: 200.930MHz)
   Minimum input arrival time before clock: 3.689ns
   Maximum output required time after clock: 4.869ns
   Maximum combinational path delay: No path found

=========================================================================


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "send.v"
Module <send> compiled
Compiling verilog file "icon_xst_example.v"
Module <icon_xst_example> compiled
Module <icon> compiled
Compiling verilog file "ila_xst_example.v"
Module <ila_xst_example> compiled
Module <ila> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
No errors in compilation
Analysis of file <"uart.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <uart>.
Module <uart> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <uart>.
Analyzing module <send>.
Module <send> is correct for synthesis.
 
Analyzing module <icon>.
Generating a Black Box for module <icon>.
 
Analyzing module <ila>.
Generating a Black Box for module <ila>.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <send>.
    Related source file is "send.v".
    Found 1-bit register for signal <data_out>.
    Found 1-bit register for signal <data_out_flag>.
    Found 1-bit register for signal <busy>.
    Found 4-bit up counter for signal <cnt>.
    Found 30-bit up counter for signal <cnt1>.
    Found 26-bit up counter for signal <cnt2>.
    Summary:
	inferred   3 Counter(s).
	inferred   3 D-type flip-flop(s).
Unit <send> synthesized.