📄 uart.pcf
字号:
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_s3/ug1_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/jo_2.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_s3/uf1_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/jo_2.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_s3/ug0_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/jo_3.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/pd_rpm/i_srl_t2/i_yes_rpm/i_s3/uf0_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns1/jo_3.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_s3/ug3_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/jo_0.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_s3/uf3_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/jo_0.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_s3/ug2_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/jo_1.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_s3/uf2_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/jo_1.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_s3/ug1_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/jo_2.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_s3/uf1_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/jo_2.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_s3/ug0_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/jo_3.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/pd_rpm/i_srl_t2/i_yes_rpm/i_s3/uf0_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_ns0/jo_3.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/pd_rpm/i_srl_t2/i_yes_rpm/ug1_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/jo_0.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/pd_rpm/i_srl_t2/i_yes_rpm/uf1_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/jo_0.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/pd_rpm/i_srl_t2/i_yes_rpm/ug0_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/jo_1.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/pd_rpm/i_srl_t2/i_yes_rpm/uf0_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scrst/jo_1.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_wce/i_srl_t2/u_srlc16e"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/scnt_ce.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_sce/i_srl_t2/u_srlc16e"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/scnt_ce.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/pd_rpm/i_srl_t2/i_yes_rpm/ug1_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/jo_0.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/pd_rpm/i_srl_t2/i_yes_rpm/uf1_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/jo_0.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/pd_rpm/i_srl_t2/i_yes_rpm/ug0_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/jo_1.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/pd_rpm/i_srl_t2/i_yes_rpm/uf0_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cmpreset/jo_1.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm/i_srl_t2/i_yes_rpm/ug1_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/i_srl_t2/icfg_data_2.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm/i_srl_t2/i_yes_rpm/uf1_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/i_srl_t2/icfg_data_2.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm/i_srl_t2/i_yes_rpm/ug0_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/cfg_data_4.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_cdone/pd_rpm/i_srl_t2/i_yes_rpm/uf0_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/cfg_data_4.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scmpce/pd_rpm/i_srl_t2/i_yes_rpm/ug_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/cfg_data_3.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_scmpce/pd_rpm/i_srl_t2/i_yes_rpm/uf_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/cfg_data_3.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_wlcmpce/pd_rpm/i_srl_t2/i_yes_rpm/ug_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/cfg_data_2.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_wlcmpce/pd_rpm/i_srl_t2/i_yes_rpm/uf_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/cfg_data_2.SLICEM_FMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_whcmpce/pd_rpm/i_srl_t2/i_yes_rpm/ug_cfglut4"
BEL
"i_ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/wcnt_hcmp_ce.SLICEM_GMC15_BLACKBOX"
BEL
"i_ila/ila/i_yes_d/u_ila/u_g2_sq/u_capctrl/i_srlt_ne_1/u_whcmpce/pd_rpm/i_srl_t2/i_yes_rpm/uf_cfglut4"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/i_rdaddr/i_ni_gt_1/ine1/u_low_count/g/3/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/i_rdaddr/i_ni_gt_1/ine1/u_low_count/g/2/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/i_rdaddr/i_ni_gt_1/ine1/u_low_count/g/1/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/i_rdaddr/i_ni_gt_1/ine1/u_low_count/g/0/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/13/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/12/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/11/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/10/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/9/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/8/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/7/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/6/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/5/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/4/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/3/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/2/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/1/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/i_rdaddr/u_hc/g/0/u_fdre"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/i_mux/g_ff/3/u_ff"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/i_mux/g_ff/2/u_ff"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/i_mux/g_ff/1/u_ff"
BEL
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/i_mux/g_ff/0/u_ff"
BEL "i_icon/icon/u_icon/u_tdi_reg" BEL "i_icon/icon/u_icon/u_tdo_reg"
BEL "i_icon/icon/u_icon/u_cmd/g_target/15/i_eq0/u_target" BEL
"i_icon/icon/u_icon/u_cmd/g_target/14/i_ne0/u_target" BEL
"i_icon/icon/u_icon/u_cmd/g_target/13/i_ne0/u_target" BEL
"i_icon/icon/u_icon/u_cmd/g_target/12/i_ne0/u_target" BEL
"i_icon/icon/u_icon/u_cmd/g_target/11/i_ne0/u_target" BEL
"i_icon/icon/u_icon/u_cmd/g_target/10/i_ne0/u_target" BEL
"i_icon/icon/u_icon/u_cmd/g_target/9/i_ne0/u_target" BEL
"i_icon/icon/u_icon/u_cmd/g_target/8/i_ne0/u_target" BEL
"i_icon/icon/u_icon/u_cmd/g_target/7/i_ne0/u_target" BEL
"i_icon/icon/u_icon/u_cmd/g_target/6/i_ne0/u_target" BEL
"i_icon/icon/u_icon/u_sync/g_sync_word/6/i_eq0/u_fdr" BEL
"i_icon/icon/u_icon/u_sync/g_sync_word/5/i_ne0/u_fdr" BEL
"i_icon/icon/u_icon/u_sync/g_sync_word/4/i_ne0/u_fdr" BEL
"i_icon/icon/u_icon/u_sync/g_sync_word/3/i_ne0/u_fdr" BEL
"i_icon/icon/u_icon/u_sync/g_sync_word/2/i_ne0/u_fdr" BEL
"i_icon/icon/u_icon/u_sync/g_sync_word/1/i_ne0/u_fdr" BEL
"i_icon/icon/u_icon/u_sync/g_sync_word/0/i_ne0/u_fdr" BEL
"i_icon/icon/u_icon/u_sync/u_sync" BEL
"i_icon/icon/u_icon/u_stat/u_stat_cnt/g/5/u_fdre" BEL
"i_icon/icon/u_icon/u_stat/u_stat_cnt/g/4/u_fdre" BEL
"i_icon/icon/u_icon/u_stat/u_stat_cnt/g/3/u_fdre" BEL
"i_icon/icon/u_icon/u_stat/u_stat_cnt/g/2/u_fdre" BEL
"i_icon/icon/u_icon/u_stat/u_stat_cnt/g/1/u_fdre" BEL
"i_icon/icon/u_icon/u_stat/u_stat_cnt/g/0/u_fdre" BEL
"i_icon/icon/u_icon/u_stat/u_tdo" PIN
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/0/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1043/RAMB16_pins<159>"
PIN
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/1/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1039/RAMB16_pins<159>"
PIN
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/2/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1035/RAMB16_pins<159>"
PIN
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/3/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1031/RAMB16_pins<159>"
PIN
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/4/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1027/RAMB16_pins<159>"
PIN
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/5/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1023/RAMB16_pins<159>"
PIN
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/6/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1019/RAMB16_pins<159>"
PIN
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/7/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1015/RAMB16_pins<159>"
PIN
"i_ila/ila/i_yes_d/u_ila/i_intcap/u_capstor/i_case1/i_rt1/u_ram/g_bram/8/u_bram/ram_rt1_s1_s4_if/ram_rt1_s1_s4_i/newSim1011/RAMB16_pins<159>";
TIMEGRP U_CLK = BEL "i_icon/icon/u_icon/u_idata_cmd";
TS_J_TO_J = MAXDELAY FROM TIMEGRP "J_CLK" TO TIMEGRP "J_CLK" 30 ns;
TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "J_CLK" 15 ns;
TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "U_CLK" 15 ns;
PATH TS_U_TO_D_path = FROM TIMEGRP "U_CLK" TO TIMEGRP "D_CLK";
PATH "TS_U_TO_D_path" TIG;
PATH TS_J_TO_D_path = FROM TIMEGRP "J_CLK" TO TIMEGRP "D_CLK";
PATH "TS_J_TO_D_path" TIG;
PATH TS_D_TO_J_path = FROM TIMEGRP "D_CLK" TO TIMEGRP "J_CLK";
PATH "TS_D_TO_J_path" TIG;
PIN i_icon/icon/u_icon/i_yes_bscan/u_bs/i_v4/u_bs_pins<3> = BEL
"i_icon/icon/u_icon/i_yes_bscan/u_bs/i_v4/u_bs" PINNAME SHIFT;
PIN "i_icon/icon/u_icon/i_yes_bscan/u_bs/i_v4/u_bs_pins<3>" TIG;
SCHEMATIC END;
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